參數(shù)資料
型號(hào)： ATF2500CQ-25GM/883
廠商： ATMEL CORP
元件分類： PLD
英文描述： EE PLD, 25 ns, CDIP40
封裝： 0.600 INCH, CERDIP-40
文件頁(yè)數(shù)： 23/34頁(yè)
文件大?。?/td> 700K
代理商： ATF2500CQ-25GM/883
3
ATF2500C Family
0777F–08/01
Power-up Reset
The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed
slightly from V
CC crossing VRST, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the uncertainty of how V
CC actually rises
in the system, the following conditions are required:
1.
The V
CC rise must be monotonic,
2.
After reset occurs, all input and feedback setup times must be met before driving the
clock pin or terms high, and
3.
The clock pin, and any signals from which clock terms are derived, must remain stable
during t
PR.
Parameter
Description
Typ
Max
Units
t
PR
Power-up Reset Time
600
1000
ns
VRST
Power-up Reset Voltage
3.8
4.5
V
Level Forced on
Odd I/O Pin during
PRELOAD Cycle
Q Select Pin
State
Even/Odd
Select
Even Q1 State
after Cycle
Even Q2 State
after Cycle
Odd Q1 State
after Cycle
Odd Q2 State
after Cycle
V
IH/VIL
Low
High/Low
X
V
IH/VIL
High
Low
X
High/Low
X
V
IH/VIL
Low
High
X
High/Low
X
V
IH/VIL
High
X
High/Low
相關(guān)PDF資料
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