參數(shù)資料
型號: ATF750C-10SC
廠商: Atmel
文件頁數(shù): 6/25頁
文件大?。?/td> 0K
描述: IC CPLD 10NS 24SOIC
標準包裝: 31
系列: ATF750C(L)
可編程類型: 系統(tǒng)內(nèi)可編程(最少 1K 次編程/擦除循環(huán))
最大延遲時間 tpd(1): 10.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
宏單元數(shù): 10
輸入/輸出數(shù): 10
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 24-SOIC W
包裝: 管件
其它名稱: ATF750C10SC
14
0776L–PLD–11/08
ATF750C(L)
29. Preload of Registered Outputs
The ATF750C(L)’s registers are provided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A V
IH level on the I/O pin will force the regis-
ter high; a V
IL will force it low, independent of the output polarity. The PRELOAD state is entered
by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When the clock
term is pulsed high, the data on the I/O pins is placed into the register chosen by the select pin
.
Level Forced on Registered
Output Pin during Preload Cycle
Select Pin
State
Register #0 State
after Cycle
Register #1 State
after Cycle
V
IH
Low
High
X
VIL
Low
X
VIH
High
X
High
V
IL
High
X
Low
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