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參數(shù)資料
| 型號： | ATF750C-7SX |
| 廠商： | Atmel |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 7NS 24SOIC |
| 標準包裝： | 31 |
| 系列： | ATF750C(L) |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 1K 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 宏單元數(shù)： | 10 |
| 輸入/輸出數(shù)： | 10 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC W |
| 包裝： | 管件 |
12
0776L–PLD–11/08
ATF750C(L)
23. Using the ATF750C’s Many Advanced Features
The ATF750C(L)’s advanced flexibility packs more usable gates into 24 pins than any other logic
device. The ATF750C(L)s start with the popular 22V10 architecture, and add several enhanced
features:
Selectable D- and T-type Registers
Each ATF750C(L) flip-flop can be individually configured as either D- or T-type. Using the T-
type configuration, JK and SR flip-flops are also easily created. These options allow more
efficient product term usage.
Selectable Asynchronous Clocks
Each of the ATF750C(L)’s flip-flops may be clocked by its own clock product term or directly
from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use the same
clock. Buried state machines, counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock source selection further allows mixing
higher performance pin clocking and flexible product term clocking within one design.
A Full Bank of Ten More Registers
The ATF750C(L) provides two flip-flops per output logic cell for a total of 20. Each register
has its own sum term, its own reset term and its own clock term.
Independent I/O Pin and Feedback Paths
Each I/O pin on the ATF750C(L) has a dedicated input path. Each of the 20 registers has its
own feedback terms into the array as well. This feature, combined with individual product
terms for each I/O’s output enable, facilitates true bi-directional I/O design.
24. Synchronous Preset and Asynchronous Reset
One synchronous preset line is provided for all 20 registers in the ATF750C(L). The appropriate
input signals to cause the internal clocks to go to a high state must be received during a syn-
chronous preset. Appropriate setup and hold times must be met, as shown in the switching
waveform diagram.
An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and
slave halves of the flip-flops are reset when the input signals received force the internal resets
high.
25. Software Support
All family members of the ATF750C(L) can be designed with Atmel
-WinCUPL.
Additionally, the ATF750C may be programmed to perform the ATV750(L) functional subset (no
T-type flip-flops, pin clocking or D/T2 feedback) using the ATV750 JEDEC file. In this case, the
ATF750C becomes a direct replacement or speed upgrade for the ATV750. The ATF750C is a
direct replacement for the ATV750(L) and the ATV750B(L).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ATF750CL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High-speed Complex Programmable Logic Device |
| ATF750CL-15GM/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ATF750CL-15JC | 功能描述:CPLD - 復雜可編程邏輯器件 750 GATE LOW POWER - 15NS 28 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF750CL-15JI | 功能描述:CPLD - 復雜可編程邏輯器件 750 GATE LOW POWER - 15NS 28 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF750CL-15JN | 功能描述:CPLD - 復雜可編程邏輯器件 ASICS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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