- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄22100 > ATF750CL-15SU (Atmel)IC PLD HS 750 GATE 5.0V 24-SOIC PDF資料下載
參數(shù)資料
| 型號(hào)： | ATF750CL-15SU |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 5/25頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD HS 750 GATE 5.0V 24-SOIC |
| 標(biāo)準(zhǔn)包裝： | 31 |
| 系列： | ATF750C(L) |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 1K 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 宏單元數(shù)： | 10 |
| 輸入/輸出數(shù)： | 10 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)
13
0776L–PLD–11/08
ATF750C(L)
26. Software Compiler Mode Selection
27. Third Party Programmer Support
Note:
1. The ATF750C has 14,504 JEDEC fuses.
28. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF750C(L) fuse patterns.
Once the security fuse is programmed, all fuses will appear programmed during verify.
The security fuse should be programmed last, as its effect is immediate.
Table 26-1.
Software Compiler Mode Selection
Device
Atmel - WinCupL Device Mnemonic
Pin-keeper
ATF750C-DIP
V750C
V750CPPK
Disabled
Enabled
ATF750C-PLCC
V750LCC
V750CPPKLCC
Disabled
Enabled
Table 27-1.
Third Party Programmer Support
Device
Description
ATF750C (V750)
V750 Cross-programming. JEDEC file compatible with standard V750 JEDEC
file (total fuses in JEDEC file = 14394). The Programmer will automatically
program “0”s into the User Rrow (UES), and disable the Pin-keeper features. The
Fuse Checksum will be the same as the old ATV750/L file. This device type is
recommended for customers that are directly migrating from an ATV750/L device
to an ATF750C/CL device.
ATF750C (V750B)
V750B Cross-programming. JEDEC file compatible with standard V750B
JEDEC file (total fuses in JEDEC file = 14435). The Programmer will
automatically program “0”s into the User Row (UES), and disable the Pin-keeper
feature. The Fuse Checksum will be the same as the old ATV750B/BL file. This
device type is recommended for customers that are directly migrating from an
ATV750B/BL device to an ATF750C/CL device.
ATF750C
Programming of User Row (UES) bits supported and Pin-keeper bit is user-
programmable. (Total fuses in JEDEC file = 14504). This is the default device
type and is recommended for users that have re-compiled their source design
files to specifically target the ATF750C device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TAP224M035DTW | CAP TANT 0.22UF 35V 20% RADIAL |
| ATF750CL-15PU | IC PLD HS 750 GATE 5.0V 24-PDIP |
| FSGM0565RBWDTU | IC OFF-LINE SWITCH PWM TO220F-6 |
| GBM18DCBN | CONN EDGECARD 36POS R/A .156 SLD |
| GRM31A5C2J471JW01D | CAP CER 470PF 630V 5% NP0 1206 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF750CL-15XC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 ASICS RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF750CL-15XU | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 750 GATE LOW POWER - 15NS RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF750LVC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High-speed Complex Programmable Logic Device |
| ATF750LVC_08 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High-speed Complex Programmable Logic Device |
| ATF750LVC-15JC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 750 GATE LOW POWER - 15NS 28 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。