參數(shù)資料
型號(hào): ATF750LVC-15SC
廠商: Atmel
文件頁(yè)數(shù): 14/19頁(yè)
文件大小: 0K
描述: IC CPLD 15NS 24SOIC
標(biāo)準(zhǔn)包裝: 31
系列: ATF750LVC
可編程類型: 系統(tǒng)內(nèi)可編程(最少 1K 次編程/擦除循環(huán))
最大延遲時(shí)間 tpd(1): 15.0ns
電壓電源 - 內(nèi)部: 3 V ~ 5.25 V
宏單元數(shù): 10
輸入/輸出數(shù): 10
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 管件
其它名稱: ATF750LVC15SC
4
1447F–PLD–11/08
ATF750LVC
8.
Bus-friendly Pin-keeper Input and I/Os
All input and I/O pins on the ATF750LVC have programmable “pin-keeper” circuits. If acti-
vated, when any pin is driven high or low and then subsequently left floating, it will stay at that
previous high or low level.
This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels,
which cause unnecessary power consumption and system noise. The keeper circuits elimi-
nate the need for external pull-up resistors and eliminate their DC power consumption.
Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the
logic compiler device selection menu. Please refer to the software compiler table for more
details. Once the pin-keeper circuits are disabled, normal termination procedures are required
for unused inputs and I/Os.
9.
Input Diagram
10. I/O Diagram
Table 1. Software Compiler Mode Selection
Synario
WinCupl
Pin-keeper Circuit
ATF750LVC
V750C
Disabled
ATF750LVC (PPK)
V750CPPK
Enabled
100K
V
CC
ESD
PROTECTION
CIRCUIT
INPUT
PROGRAMMABLE
OPTION
100K
V
CC
V
CC
DATA
OE
I/O
PROGRAMMABLE
OPTION
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