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參數(shù)資料
| 型號： | ATH18K12-9S |
| 英文描述： | 18-A, 12-V Input Non-Isolated Wide-Output Adjust Power Module |
| 中文描述： | 18甲，12 V輸入非隔離寬輸出調(diào)節(jié)電源模塊 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 1470K |
| 代理商： | ATH18K12-9S |
Application Notes
ATH Series of Wide-Output Adjust
Power Modules (12-V Input)
North America (USA): 1-888-41-ASTEC Europe (UK): 44(1384)842-211 Asia (HK): 852-2437-9662
Margin Up/Down Controls
The ATH10 (10A), ATH12/15 (12/15A), ATH18/22 (18/
22A), and ATH26/30 (26/30A) products incorporate
Margin
Up
and
Margin Down
control inputs. These controls allow
the output voltage to be momentarily adjusted
1
, either up
or down, by a nominal 5 %. This provides a convenient
method for dynamically testing the operation of the load
circuit over its supply margin or range. It can also be used to
verify the function of supply voltage supervisors. The
±5 % change is applied to the adjusted output voltage, as set
by the external resistor, R
set
at the
V
o
Adjust
pin.
The 5 % adjustment is made by pulling the appropriate
margin control input directly to the
GND
terminal
2
.
A low-leakage open-drain device, such as an n-channel
MOSFET or p-channel JFET is recommended for this
purpose
3
. Adjustments of less than 5 % can also be accom-
modated by adding series resistors to the control inputs
(See Figure 3-4). The value of the resistor can be selected
from Table 3-2, or calculated using the following formula.
Up/Down Adjust Resistance Calculation
To reduce the margin adjustment to something less than
5 %, series resistors are required (See R
D
and R
U
in
Figure 3-7). For the same amount of adjustment, the
resistor value calculated for R
U
and R
D
will be the same.
The formulas is as follows.
R
U
or R
D
=
499
%
– 99.8
k
Where
% = The desired amount of margin adjust in
percent.
Notes:
1. The
Margin Up*
and
Margin Dn*
controls were not
intended to be activated simultaneously. If they are
their affects on the output voltage may not completely
cancel, resulting in the possibility of a slightly higher
error in the output voltage set point.
2. The ground reference should be a direct connection to
the module
GND
at pin 7 (pin 1 for the ATH06).
This will produce a more accurate adjustment at the
load circuit terminals. The transistors Q
1
and Q
2
should
be located close to the regulator.
3. The Margin Up and Margin Dn control inputs are not
compatible with devices that source voltage. This includes
TTL logic. These are analog inputs and should only be
controlled with a true open-drain device (preferably
a discrete MOSFET transistor). The device selected
should have low off-state leakage current. Each input
sources 8 μA when grounded, and has an open-circuit
voltage of 0.8 V.
Figure 3-7; Margin Up/Down Application Schematic
Table 3-2; Margin Up/Down Resistor Values
% Adjust
5
4
3
2
1
R
U
/ R
D
0.0 k
24.9 k
66.5 k
150.0 k
397.0 k
C
out
+
C
in
V
IN
GND
MargDn
L
O
A
D
Q
2
+V
OUT
Q
1
+
MargUp
0V
+V
o
R
D
R
U
PTH05010W
(Top View)
1
2
10
9
8
7
6
5
4
3
GND
R
0.1 W, 1 %
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