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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ATMEGA128L-8MNR |
| 寤犲晢锛� | Atmel |
| 鏂囦欢闋佹暩(sh霉)锛� | 19/24闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | MCU AVR 128KB FLASH 8MHZ 64QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | megaAVR Introduction |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | AVR® ATmega |
| 鏍稿績铏曠悊鍣細 | AVR |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 8MHz |
| 閫ｉ€氭€э細 | EBI/EMI锛孖²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 53 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 128KB锛�64K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 4K x 8 |
| RAM 瀹归噺锛� | 4K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 64-VFQFN 瑁搁湶鐒婄洡 |
| 鍖呰锛� | 鍓垏甯� (CT) |
| 鍏跺畠鍚嶇ū锛� | ATMEGA128L-8MNRCT |
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ATmega128
The Atmel AVR core combines a rich instruction set with 32 general purpose working regis-
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction executed in one clock cycle. The
resulting architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The ATmega128 provides the following features: 128Kbytes of In-System Programmable Flash
with Read-While-Write capabilities, 4Kbytes EEPROM, 4Kbytes SRAM, 53 general purpose I/O
lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Coun-
ters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-
channel, 10-bit ADC with optional differential input stage with programmable gain, programma-
ble Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant
JTAG test interface, also used for accessing the On-chip Debug system and programming and
six software selectable power saving modes. The Idle mode stops the CPU while allowing the
SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down
mode saves the register contents but freezes the Oscillator, disabling all other chip functions
until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer contin-
ues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous
Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the
Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very
fast start-up combined with low power consumption. In Extended Standby mode, both the main
Oscillator and the Asynchronous Timer continue to run.
Atmel offers the QTouch library for embedding capacitive touch buttons, sliders and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers
robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key
Suppression (AKS) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.
The device is manufactured using Atmel鈥檚 high-density nonvolatile memory technology. The On-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effec-
tive solution to many embedded control applications.
The ATmega128 device is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.
ATmega103 and
ATmega128
Compatibility
The ATmega128 is a highly complex microcontroller where the number of I/O locations super-
sedes the 64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility
with the ATmega103, all I/O locations present in ATmega103 have the same location in
ATmega128. Most additional I/O locations are added in an Extended I/O space starting from $60
to $FF, (i.e., in the ATmega103 internal RAM space). These locations can be reached by using
LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relo-
cation of the internal RAM space may still be a problem for ATmega103 users. Also, the
increased number of interrupt vectors might be a problem if the code uses absolute addresses.
To solve these problems, an ATmega103 compatibility mode can be selected by programming
the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the
internal RAM is located as in ATmega103. Also, the Extended Interrupt vectors are removed.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VI-J51-IW-F1 | CONVERTER MOD DC/DC 12V 100W |
| VI-BTN-IW-F4 | CONVERTER MOD DC/DC 18.5V 100W |
| MS27484T24F61P | CONN PLUG 61POS STRAIGHT W/PINS |
| DS8500-JND+ | IC MODEM HART SGL 3.6V 20-TQFN |
| D38999/20JA98HA | CONN RCPT 3POS WALL MNT W/PINS |
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鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ATmega128L-8MU | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 128kB Flash 4kB EEPROM 53 I/O Pins RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA128L-8MU 10122 | 鍒堕€犲晢:Atmel Corporation 鍔熻兘鎻忚堪: |
| ATMEGA128L-8MUR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR,128KB FLASH 4KB EE,4KB SRAM,8MHZ RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA128L-D-11 | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU Microcontroller RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA128L-W | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU Microcontroller RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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