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參數(shù)資料
| 型號(hào)： | ATMEGA163(L) |
| 英文描述： | ATmega163(L) Summary [Updated 02/03. 18 Pages] |
| 中文描述： | ATmega163（長）摘要[更新02/03。 18頁] |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 342K |
| 代理商： | ATMEGA163(L) |
5
ATmega8(L)
2486LS–AVR–10/03
Pin Descriptions
VCC
Digital supply voltage.
GND
Ground.
Port B (PB7..PB0) XTAL1/
XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the invert-
ing Oscillator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the
inverting Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as
TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in “Alternate Functions of Port B”
on page 56 and “System Clock and Clock Options” on page 23.
Port C (PC5..PC0)
Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electri-
cal characteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on
this pin for longer than the minimum pulse length will generate a Reset, even if the clock
is not running. The minimum pulse length is given in Table 15 on page 36. Shorter
pulses are not guaranteed to generate a Reset.
The various special features of Port C are elaborated on page 59.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega8 as listed on
page 61.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
15 on page 36. Shorter pulses are not guaranteed to generate a reset.
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