參數(shù)資料
型號： ATMEGA168V-10MI
廠商： Atmel
文件頁數(shù)： 5/36頁
文件大?。?/td> 0K
描述： IC AVR MCU 16K 10MHZ 32-QFN
產(chǎn)品培訓(xùn)模塊： megaAVR Introduction
標準包裝： 490
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 23
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-VFQFN 裸露焊盤
包裝： 托盤
13
2545TS–AVR–05/11
ATmega48/88/168
8.
Instruction set summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two registers
Rd
← Rd + Rr
Z, C, N, V, H
1
ADC
Rd, Rr
Add with carry two registers
Rd
← Rd + Rr + C
Z, C, N, V, H
1
ADIW
Rdl,K
Add immediate to word
Rdh:Rdl
← Rdh:Rdl + K
Z, C, N, V, S
2
SUB
Rd, Rr
Subtract two registers
Rd
← Rd - Rr
Z, C, N, V, H
1
SUBI
Rd, K
Subtract constant from register
Rd
← Rd - K
Z, C, N, V, H
1
SBC
Rd, Rr
Subtract with carry two registers
Rd
← Rd - Rr - C
Z, C, N, V, H
1
SBCI
Rd, K
Subtract with carry constant from reg.
Rd
← Rd - K - C
Z, C, N, V, H
1
SBIW
Rdl,K
Subtract immediate from Word
Rdh:Rdl
← Rdh:Rdl - K
Z, C, N, V, S
2
AND
Rd, Rr
Logical AND registers
Rd
← Rd Rr
Z, N, V
1
ANDI
Rd, K
Logical AND register and constant
Rd
← Rd K
Z, N, V
1
OR
Rd, Rr
Logical OR registers
Rd
← Rd v Rr
Z, N, V
1
ORI
Rd, K
Logical OR register and constant
Rd
← Rd v K
Z, N, V
1
EOR
Rd, Rr
Exclusive OR registers
Rd
← Rd ⊕ Rr
Z, N, V
1
COM
Rd
One’s complement
Rd
← 0xFF Rd
Z, C, N, V
1
NEG
Rd
Two’s complement
Rd
← 0x00 Rd
Z, C, N, V, H
1
SBR
Rd,K
Set bit(s) in register
Rd
← Rd v K
Z, N, V
1
CBR
Rd,K
Clear bit(s) in register
Rd
← Rd (0xFF - K)
Z, N, V
1
INC
Rd
Increment
Rd
← Rd + 1
Z, N, V
1
DEC
Rd
Decrement
Rd
← Rd 1
Z, N, V
1
TST
Rd
Test for zero or minus
Rd
← Rd Rd
Z, N, V
1
CLR
Rd
Clear register
Rd
← Rd ⊕ Rd
Z, N, V
1
SER
Rd
Set register
Rd
← 0xFF
None
1
MUL
Rd, Rr
Multiply unsigned
R1:R0
← Rd x Rr
Z, C
2
MULS
Rd, Rr
Multiply signed
R1:R0
← Rd x Rr
Z, C
2
MULSU
Rd, Rr
Multiply signed with unsigned
R1:R0
← Rd x Rr
Z, C
2
FMUL
Rd, Rr
Fractional multiply unsigned
R1:R0
← (Rd x Rr)
<< 1
Z, C
2
FMULS
Rd, Rr
Fractional multiply signed
R1:R0
← (Rd x Rr)
<< 1
Z, C
2
FMULSU
Rd, Rr
Fractional multiply signed with unsigned
R1:R0
← (Rd x Rr)
<< 1
Z, C
2
BRANCH INSTRUCTIONS
RJMP
k
Relative jump
PC
← PC + k + 1
None
2
IJMP
Indirect jump to (Z)
PC
← Z
None
2
JMP(1)
k
Direct jump
PC
← kNone
3
RCALL
k
Relative subroutine call
PC
← PC + k + 1
None
3
ICALL
Indirect call to (Z)
PC
← ZNone
3
CALL(1)
k
Direct subroutine call
PC
← kNone
4
RET
Subroutine return
PC
← STACK
None
4
RETI
Interrupt return
PC
← STACK
I
4
CPSE
Rd,Rr
Compare, skip if equal
if (Rd = Rr) PC
← PC + 2 or 3
None
1/2/3
CP
Rd,Rr
Compare
Rd
Rr
Z, N, V, C, H
1
CPC
Rd,Rr
Compare with carry
Rd
Rr C
Z, N, V, C, H
1
CPI
Rd,K
Compare register with immediate
Rd
K
Z, N, V, C, H
1
SBRC
Rr, b
Skip if bit in register cleared
if (Rr(b)=0) PC
← PC + 2 or 3
None
1/2/3
SBRS
Rr, b
Skip if bit in register is set
if (Rr(b)=1) PC
← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if bit in I/O register cleared
if (P(b)=0) PC
← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if bit in I/O register is set
if (P(b)=1) PC
← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if status flag set
if (SREG(s) = 1) then PC
←PC+k + 1
None
1/2
BRBC
s, k
Branch if status flag cleared
if (SREG(s) = 0) then PC
←PC+k + 1
None
1/2
BREQ
k
Branch if equal
if (Z = 1) then PC
← PC + k + 1
None
1/2
BRNE
k
Branch if not equal
if (Z = 0) then PC
← PC + k + 1
None
1/2
BRCS
k
Branch if carry set
if (C = 1) then PC
← PC + k + 1
None
1/2
BRCC
k
Branch if carry cleared
if (C = 0) then PC
← PC + k + 1
None
1/2
BRSH
k
Branch if same or higher
if (C = 0) then PC
← PC + k + 1
None
1/2
BRLO
k
Branch if lower
if (C = 1) then PC
← PC + k + 1
None
1/2
BRMI
k
Branch if minus
if (N = 1) then PC
← PC + k + 1
None
1/2
BRPL
k
Branch if plus
if (N = 0) then PC
← PC + k + 1
None
1/2
BRGE
k
Branch if greater or equal, signed
if (N
⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if less than zero, signed
if (N
⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if half carry flag set
if (H = 1) then PC
← PC + k + 1
None
1/2
BRHC
k
Branch if half carry flag cleared
if (H = 0) then PC
← PC + k + 1
None
1/2
BRTS
k
Branch if T flag set
if (T = 1) then PC
← PC + k + 1
None
1/2
BRTC
k
Branch if T flag cleared
if (T = 0) then PC
← PC + k + 1
None
1/2
BRVS
k
Branch if overflow flag is set
if (V = 1) then PC
← PC + k + 1
None
1/2
BRVC
k
Branch if overflow flag is cleared
if (V = 0) then PC
← PC + k + 1
None
1/2
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