參數(shù)資料
型號: ATMEGA16L-8AI
廠商: Atmel
文件頁數(shù): 23/23頁
文件大?。?/td> 0K
描述: IC AVR MCU 16K LV 8MHZ IND44TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 160
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 512 x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
9
2466TS–AVR–07/10
ATmega16(L)
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd
← Rd + Rr
Z,C,N,V,H
1
ADC
Rd, Rr
Add with Carry two Registers
Rd
← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl
← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd
← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd
← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd
← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd
← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl
← Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd
← Rd Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd
← Rd K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd
← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd
← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd
← Rd ⊕ Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd
← $FF Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd
← $00 Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd
← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd
← Rd ($FF - K)
Z,N,V
1
INC
Rd
Increment
Rd
← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd
← Rd 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd
← Rd Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd
← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd
← $FF
None
1
MUL
Rd, Rr
Multiply Unsigned
R1:R0
← Rd x Rr
Z,C
2
MULS
Rd, Rr
Multiply Signed
R1:R0
← Rd x Rr
Z,C
2
MULSU
Rd, Rr
Multiply Signed with Unsigned
R1:R0
← Rd x Rr
Z,C
2
FMUL
Rd, Rr
Fractional Multiply Unsigned
R1:R0
← (Rd x Rr)
<< 1
Z,C
2
FMULS
Rd, Rr
Fractional Multiply Signed
R1:R0
← (Rd x Rr)
<< 1
Z,C
2
FMULSU
Rd, Rr
Fractional Multiply Signed with Unsigned
R1:R0
← (Rd x Rr)
<< 1
Z,C
2
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
PC
← PC + k + 1
None
2
IJMP
Indirect Jump to (Z)
PC
← Z
None
2
JMP
k
Direct Jump
PC
← kNone
3
RCALL
k
Relative Subroutine Call
PC
← PC + k + 1
None
3
ICALL
Indirect Call to (Z)
PC
← ZNone
3
CALL
k
Direct Subroutine Call
PC
← kNone
4
RET
Subroutine Return
PC
← STACK
None
4
RETI
Interrupt Return
PC
← STACK
I
4
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC
← PC + 2 or 3
None
1 / 2 / 3
CP
Rd,Rr
Compare
Rd
Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd
Rr C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd
K
Z, N,V,C,H
1
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC
← PC + 2 or 3
None
1 / 2 / 3
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC
← PC + 2 or 3
None
1 / 2 / 3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC
← PC + 2 or 3
None
1 / 2 / 3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC
← PC + 2 or 3
None
1 / 2 / 3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC
←PC+k + 1
None
1 / 2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC
←PC+k + 1
None
1 / 2
BREQ
k
Branch if Equal
if (Z = 1) then PC
← PC + k + 1
None
1 / 2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC
← PC + k + 1
None
1 / 2
BRCS
k
Branch if Carry Set
if (C = 1) then PC
← PC + k + 1
None
1 / 2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC
← PC + k + 1
None
1 / 2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC
← PC + k + 1
None
1 / 2
BRLO
k
Branch if Lower
if (C = 1) then PC
← PC + k + 1
None
1 / 2
BRMI
k
Branch if Minus
if (N = 1) then PC
← PC + k + 1
None
1 / 2
BRPL
k
Branch if Plus
if (N = 0) then PC
← PC + k + 1
None
1 / 2
BRGE
k
Branch if Greater or Equal, Signed
if (N
⊕ V= 0) then PC ← PC + k + 1
None
1 / 2
BRLT
k
Branch if Less Than Zero, Signed
if (N
⊕ V= 1) then PC ← PC + k + 1
None
1 / 2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC
← PC + k + 1
None
1 / 2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC
← PC + k + 1
None
1 / 2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC
← PC + k + 1
None
1 / 2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC
← PC + k + 1
None
1 / 2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC
← PC + k + 1
None
1 / 2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC
← PC + k + 1
None
1 / 2
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