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參數(shù)資料
| 型號： | ATMEGA32(L) |
| 英文描述： | ATmega32(L) Preliminary Summary [Updated 9/03. 18 Pages] |
| 中文描述： | ATmega32（長）的初步總結(jié)[更新9 / 03。 18頁] |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 342K |
| 代理商： | ATMEGA32(L) |
9
ATmega8(L)
2486LS–AVR–10/03
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
ORI
EOR
COM
NEG
SBR
CBR
INC
DEC
TST
CLR
SER
MUL
MULS
MULSU
FMUL
FMULS
FMULSU
BRANCH INSTRUCTIONS
RJMP
IJMP
RCALL
ICALL
RET
RETI
CPSE
CP
CPC
CPI
SBRC
SBRS
SBIC
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
Mnemonics
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Rd
Rd,K
Rd,K
Rd
Rd
Rd
Rd
Rd
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Add two Registers
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Multiply Unsigned
Multiply Signed
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Rd
←
Rd + Rr
Rd
←
Rd + Rr + C
Rdh:Rdl
←
Rdh:Rdl + K
Rd
←
Rd - Rr
Rd
←
Rd - K
Rd
←
Rd - Rr - C
Rd
←
Rd - K - C
Rdh:Rdl
←
Rdh:Rdl - K
Rd
←
Rd
Rr
Rd
←
Rd
K
Rd
←
Rd v Rr
Rd
←
Rd v K
Rd
←
Rd
⊕
Rr
Rd
←
0xFF
Rd
Rd
←
0x00
Rd
Rd
←
Rd v K
Rd
←
Rd
(0xFF - K)
Rd
←
Rd + 1
Rd
←
Rd
1
Rd
←
Rd
Rd
Rd
←
Rd
⊕
Rd
Rd
←
0xFF
R1:R0
←
Rd x Rr
R1:R0
←
Rd x Rr
R1:R0
←
Rd x Rr
R1:R0
←
(Rd x Rr)
<< 1
R1:R0
←
(Rd x Rr)
<< 1
R1:R0
←
(Rd x Rr)
<< 1
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
Z,C
Z,C
Z,C
Z,C
Z,C
Z,C
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
k
Relative Jump
Indirect Jump to (Z)
Relative Subroutine Call
Indirect Call to (Z)
Subroutine Return
Interrupt Return
Compare, Skip if Equal
Compare
Compare with Carry
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
PC
←
PC + k + 1
PC
←
Z
PC
←
PC + k + 1
PC
←
Z
PC
←
STACK
PC
←
STACK
if (Rd = Rr) PC
←
PC + 2 or 3
Rd
Rr
Rd
Rr
C
Rd
K
if (Rr(b)=0) PC
←
PC + 2 or 3
if (Rr(b)=1) PC
←
PC + 2 or 3
if (P(b)=0) PC
←
PC + 2 or 3
if (P(b)=1) PC
←
PC + 2 or 3
if (SREG(s) = 1) then PC
←
PC+k + 1
if (SREG(s) = 0) then PC
←
PC+k + 1
if (Z = 1) then PC
←
PC + k + 1
if (Z = 0) then PC
←
PC + k + 1
if (C = 1) then PC
←
PC + k + 1
if (C = 0) then PC
←
PC + k + 1
if (C = 0) then PC
←
PC + k + 1
if (C = 1) then PC
←
PC + k + 1
if (N = 1) then PC
←
PC + k + 1
if (N = 0) then PC
←
PC + k + 1
if (N
⊕
V= 0) then PC
←
PC + k + 1
if (N
⊕
V= 1) then PC
←
PC + k + 1
if (H = 1) then PC
←
PC + k + 1
if (H = 0) then PC
←
PC + k + 1
if (T = 1) then PC
←
PC + k + 1
if (T = 0) then PC
←
PC + k + 1
if (V = 1) then PC
←
PC + k + 1
if (V = 0) then PC
←
PC + k + 1
Operation
None
None
None
None
None
I
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Flags
2
2
3
3
4
4
k
Rd,Rr
Rd,Rr
Rd,Rr
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
1 / 2 / 3
1
1
1
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
#Clocks
Operands
Description
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