參數(shù)資料
型號: ATMEGA325-16AI
廠商: Atmel
文件頁數(shù): 21/29頁
文件大?。?/td> 0K
描述: IC AVR MCU 32K 16MHZ 64TQFP
產(chǎn)品培訓模塊: megaAVR Introduction
標準包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: SPI,UART/USART,USI
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
PCA9698
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 3 August 2010
28 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
The programming becomes effective at the Acknowledge.
If more than 1 byte is written, previous data is overwritten.
Fig 18. Write to the output structure configuration, all bank control, or mode selection
002aab947
S A6 A5 A4 A3 A2 A1 A0 0 A
slave address
R/W
START condition
command register
AI = 'don't care'
A
acknowledge
from slave
DATA
A
acknowledge
from slave
acknowledge
from slave
P
STOP condition
SDA
X
01010 D1 D0
00 for output structure configuration programming
01 for all bank control register programming
10 for mode selection register programming
If AI = 0, the same register is read during the whole sequence.
If AI = 1, the register value is incremented after each read. When the last register bank is read, it rolls over to the first byte of the
category (see category definition in Section 7.3 “Command register”).
The INT signal is released only when the last register containing an input that changed has been read. For example, when
IO2_4 and IO4_7 change at the same time and an Input Port register read sequence is initiated, starting with IP0, INT is
released after IP4 is read (and not after IP2 is read).
Fig 19. Read from Input Port, Output Port, I/O Configuration, Polarity Inversion, or Mask interrupt registers
002aab948
S A6 A5 A4 A3 A2 A1 A0 0 A
slave address
R/W
START condition
command register
AI = 1
A
acknowledge
from slave
A
no acknowledge
from master
acknowledge
from slave
P
STOP condition
SDA
1
0 D5 D4 D3 D2 D1 D0
Sr
repeated START
condition
A6 A5 A4 A3 A2 A1 A0
slave address
1 A
R/W
acknowledge
from slave
data from register
DATA
A
acknowledge
from master
first byte
register determined
by D4 D3 D2 D1 D0
data from register
DATA
second byte
data from register
DATA
last byte
D[5:0] = 00 1000 for Output Port register bank 0
D[5:0] = 01 0000 for Polarity Inversion register bank 0
D[5:0] = 01 1000 for Configuration register bank 0
D[5:0] = 00 0000 for Input Port register bank 0
D[5:0] = 10 0000 for Mask Interrupt register bank 0
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