參數(shù)資料
型號(hào): ATMEGA325V-8AI
廠商: Atmel
文件頁(yè)數(shù): 20/29頁(yè)
文件大?。?/td> 0K
描述: IC AVR MCU 32K 8MHZ 64TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART,USI
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤(pán)
PCA9698
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 3 August 2010
27 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
OE is LOW (with OEPOL = 0) or HIGH (with OEPOL = 1) to observe a change in the outputs.
OCH = 0. When OCH = 1, the change in the port happens at the acknowledge phase.
Two, three, or four adjacent banks can be programmed by using the Auto-Increment feature (AI = 1) and change at the
corresponding output port becomes effective at the STOP command when OCH = 0, or at each acknowledge when OCH = 1.
Fig 16. Write to a specific output port
002aab945
S A6 A5 A4 A3 A2 A1 A0 0 A
slave address
R/W
START condition
A
acknowledge
from slave
DATA BANK X
P
STOP
condition
A
SDA
tv(Q)
write to port
data out from port
data X valid
AI
0001 D2 D1 D0
acknowledge
from slave
acknowledge
from slave
bank X
determined by
D2, D1, D0
The programing becomes effective at the Acknowledge.
Less than 5 bytes can be programmed by using the same scheme. ‘D5 D4 D3 D2 D1 D0’ refers to the first register to be
programmed.
If more than 5 bytes are written, previous data are overwritten (the sixth configuration register will roll over to the first addressed
configuration register, the sixth Polarity Inversion register will roll over to the first addressed Polarity Inversion register, the sixth
Mask interrupt register will roll over to the first addressed Mask interrupt register.
Fig 17. Write to the I/O Configuration, Polarity Inversion, or Mask interrupt registers (5 banks)
002aab946
S A6 A5 A4 A3 A2 A1 A0 0 A
slave address
R/W
START condition
command register
AI = 1
A
acknowledge
from slave
DATA BANK 0 A
acknowledge
from slave
DATA BANK 1
acknowledge
from slave
A
acknowledge
from slave
DATA BANK 2 A
acknowledge
from slave
DATA BANK 3 A
acknowledge
from slave
DATA BANK 4
P
STOP
condition
A
SDA
1
0 D5 D4 D3 D2 D1 D0
01 0000 for Polarity Inversion register programming bank 0
01 1000 for Configuration register programming bank 0
10 0000 for Mask interrupt register programming bank 0
acknowledge
from slave
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