參數(shù)資料
型號: ATMEGA3290V-8AI
廠商: Atmel
文件頁數(shù): 24/30頁
文件大?。?/td> 0K
描述: IC AVR MCU 32K 8MHZ 100TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART,USI
外圍設(shè)備: 欠壓檢測/復(fù)位,LCD,POR,PWM,WDT
輸入/輸出數(shù): 69
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
配用: ATSTK600-TQFP100-ND - STK600 SOCKET/ADAPTER 100-TQFP
ATSTK504-ND - STARTER KIT AVR EXP MOD 100P LCD
SC28L92_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 19 December 2007
30 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
5
-
Channel A transmitter Request To Send (RTS) control.
0 = No RTS control
1 = RTS control
This bit controls the deactivation of the RTSAN output (OP0) by the
transmitter. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR2A[5] = 1 caused OPR[0] to be reset
automatically one bit time after the characters in the channel A transmit
shift register and in the Tx FIFO, if any, are completely transmitted
including the programmed number of stop bits, if the transmitter is not
enabled
This feature can be used to automatically terminate the transmission of a
message as follows (line turnaround):
1. Program auto-reset mode: MR2A[5] = 1
2. Enable transmitter
3. Assert RTSAN: OPR[0] = 1
4. Send message
5. Disable transmitter after the last character is loaded into the channel A
Tx FIFO
6. The last character will be transmitted and OPR[0] will be reset one bit
time after the last stop bit, causing RTSAN to be negated
4
-
Channel A transmitter Clear To Send (CTS) control.
0 = Input CTSAN(IP0) has no effect on the transmitter
1 = CTS control enabled
If this bit is a 1, the transmitter checks the state of CTSAN (IP0) each time
it is ready to send a character. If IP0 is asserted (LOW), the character is
transmitted. If it is negated (HIGH), the TxDA output remains in the
marking state and the transmission is delayed until CTSAN goes LOW.
Changes in CTSAN while a character is being transmitted do not affect the
transmission of that character.
3 to 0
-
Stop bit length select. This eld programs the length of the stop bit
appended to the transmitted character. Stop bit lengths of 9
16 to 1 and
1
9
16 to 2 bits, in increments of
1
16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1
1
16 to 2
stop bits can be programmed in increments of 1
16 bit. In all cases, the
receiver only checks for a mark condition at the center of the stop bit
position (one half-bit time after the last data bit, or after the parity bit if
enabled is sampled). Refer to Table 32 for the values.
If an external 1
× clock is used for the transmitter:
MR2A[3] = 0 selects one stop bit
MR2A[3] = 1 selects two stop bits
Table 30.
MR2A - Mode Register 2 channel A (address 0x0) bit description …continued
Bit
Symbol
Description
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