2011 Microchip Technology Inc.
Preliminary
DS41569A-page 127
PIC16LF1904/6/7
TABLE 15-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
FIGURE 15-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
Clock Source
ADCS<2:0>
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
FOSC/2
000
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0
s
FOSC/4
100
200 ns(2)
250 ns(2)
500 ns(2)
1.0
s4.0 s
FOSC/8
001
400 ns(2)
0.5
s(2)
1.0
s2.0 s
8.0
s(3)
FOSC/16
101
800 ns
1.0
s2.0 s4.0 s
16.0
s(3)
FOSC/32
010
1.6
s2.0 s4.0 s
8.0
s(3)
32.0
s(3)
FOSC/64
110
3.2
s4.0 s
8.0
s(3)
16.0
s(3)
64.0
s(3)
FRC
x11
1.0-6.0
s(1,4)
1.0-6.0
s(1,4)
1.0-6.0
s(1,4)
1.0-6.0
s(1,4)
1.0-6.0
s(1,4)
Legend:
Shaded cells are outside of recommended range.
Note
1:
The FRC source has a typical TAD time of 1.6
s for VDD.
2:
These values violate the minimum required TAD time.
3:
For faster conversion times, the selection of another clock source is recommended.
4:
The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8
TAD11
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10
TCY - TAD
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
On the following cycle: