參數(shù)資料
型號(hào)： ATMEGA48V-10AU
廠商： Atmel
文件頁數(shù)： 6/36頁
文件大?。?/td> 0K
描述： IC AVR MCU 4K 10MHZ 1.8V 32TQFP
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
megaAVR Introduction
標(biāo)準(zhǔn)包裝： 250
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 23
程序存儲(chǔ)器容量： 4KB（2K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 613 (CN2011-ZH PDF)
配用： ATSTK600-RC29-ND - STK600 ROUTING CARD AVR
ATSTK600-TQFP32-ND - STK600 SOCKET/ADAPTER 32-TQFP
ATSTK600-DIP40-ND - STK600 SOCKET/ADAPTER 40-PDIP
ATAVRDRAGON-ND - KIT DRAGON FLASH MEM AVR
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATJTAGICE2-ND - AVR ON-CHIP D-BUG SYSTEM
14
2545TS–AVR–05/11
ATmega48/88/168
BRIE
k
Branch if interrupt enabled
if ( I = 1) then PC
← PC + k + 1
None
1/2
BRID
k
Branch if interrupt disabled
if ( I = 0) then PC
← PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set bit in I/O register
I/O(P,b)
← 1None
2
CBI
P,b
Clear bit in I/O register
I/O(P,b)
← 0None
2
LSL
Rd
Logical shift left
Rd(n+1)
← Rd(n), Rd(0) ← 0
Z, C, N, V
1
LSR
Rd
Logical shift right
Rd(n)
← Rd(n+1), Rd(7) ← 0
Z, C, N, V
1
ROL
Rd
Rotate left through carry
Rd(0)
←C,Rd(n+1)← Rd(n),C←Rd(7)
Z, C, N, V
1
ROR
Rd
Rotate right through carry
Rd(7)
←C,Rd(n)← Rd(n+1),C←Rd(0)
Z, C, N, V
1
ASR
Rd
Arithmetic shift right
Rd(n)
← Rd(n+1), n=0..6
Z, C, N, V
1
SWAP
Rd
Swap nibbles
Rd(3..0)
←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag set
SREG(s)
← 1
SREG(s)
1
BCLR
s
Flag clear
SREG(s)
← 0
SREG(s)
1
BST
Rr, b
Bit store from register to T
T
← Rr(b)
T
1
BLD
Rd, b
Bit load from T to register
Rd(b)
← TNone
1
SEC
Set carry
C
← 1C
1
CLC
Clear carry
C
← 0
C
1
SEN
Set negative flag
N
← 1N
1
CLN
Clear negative flag
N
← 0
N
1
SEZ
Set zero flag
Z
← 1Z
1
CLZ
Clear zero flag
Z
← 0
Z
1
SEI
Global interrupt enable
I
← 1I
1
CLI
Global interrupt disable
I
← 0
I
1
SES
Set signed test flag
S
← 1S
1
CLS
Clear signed test flag
S
← 0
S
1
SEV
Set Twos complement overflow
V
← 1V
1
CLV
Clear Twos complement overflow
V
← 0
V
1
SET
Set T in SREG
T
← 1T
1
CLT
Clear T in SREG
T
← 0
T
1
SEH
Set half carry flag in SREG
H
← 1H
1
CLH
Clear half carry flag in SREG
H
← 0
H
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move between registers
Rd
← Rr
None
1
MOVW
Rd, Rr
Copy register Word
Rd+1:Rd
← Rr+1:Rr
None
1
LDI
Rd, K
Load immediate
Rd
← KNone
1
LD
Rd, X
Load indirect
Rd
← (X)
None
2
LD
Rd, X+
Load indirect and post-inc.
Rd
← (X), X ← X + 1
None
2
LD
Rd, - X
Load indirect and pre-dec.
X
← X - 1, Rd ← (X)
None
2
LD
Rd, Y
Load indirect
Rd
← (Y)
None
2
LD
Rd, Y+
Load indirect and post-inc.
Rd
← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load indirect and pre-dec.
Y
← Y - 1, Rd ← (Y)
None
2
LDD
Rd,Y+q
Load indirect with displacement
Rd
← (Y + q)
None
2
LD
Rd, Z
Load indirect
Rd
← (Z)
None
2
LD
Rd, Z+
Load indirect and post-inc.
Rd
← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load indirect and pre-dec.
Z
← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load indirect with displacement
Rd
← (Z + q)
None
2
LDS
Rd, k
Load direct from SRAM
Rd
← (k)
None
2
ST
X, Rr
Store indirect
(X)
← Rr
None
2
ST
X+, Rr
Store indirect and post-inc.
(X)
← Rr, X ← X + 1
None
2
ST
- X, Rr
Store indirect and pre-dec.
X
← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store indirect
(Y)
← Rr
None
2
ST
Y+, Rr
Store indirect and post-inc.
(Y)
← Rr, Y ← Y + 1
None
2
ST
- Y, Rr
Store indirect and pre-dec.
Y
← Y - 1, (Y) ← Rr
None
2
STD
Y+q,Rr
Store indirect with displacement
(Y + q)
← Rr
None
2
ST
Z, Rr
Store indirect
(Z)
← Rr
None
2
ST
Z+, Rr
Store indirect and post-inc.
(Z)
← Rr, Z ← Z + 1
None
2
ST
-Z, Rr
Store indirect and pre-dec.
Z
← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store indirect with displacement
(Z + q)
← Rr
None
2
STS
k, Rr
Store direct to SRAM
(k)
← Rr
None
2
LPM
Load program memory
R0
← (Z)
None
3
LPM
Rd, Z
Load program memory
Rd
← (Z)
None
3
LPM
Rd, Z+
Load program memory and post-inc
Rd
← (Z), Z ← Z+1
None
3
SPM
Store program memory
(Z)
← R1:R0
None
-
IN
Rd, P
In port
Rd
← PNone
1
OUT
P, Rr
Out port
P
← Rr
None
1
PUSH
Rr
Push register on stack
STACK
← Rr
None
2
Mnemonics
Operands
Description
Operation
Flags
#Clocks
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ATMEGA48V-10AU SL383 制造商:Atmel Corporation 功能描述:MCU 8-bit ATmega AVR RISC 4KB Flash 2.5V/3.3V/5V 32-Pin TQFP T/R 制造商:Atmel Corporation 功能描述:MCU 8BIT ATMEGA RISC 4KB FLASH 2.5V/3.3V/5V 32TQFP - Tape and Reel
ATMEGA48V-10AUR 功能描述:8位微控制器 -MCU AVR 4KB FLSH 256B EE 512B RAM-10MHZ 1.8V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ATMEGA48V10MI 制造商:Atmel Corporation 功能描述:
ATmega48V-10MI 功能描述:8位微控制器 -MCU AVR 4K FLASH 256B EE 512B SRAM ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ATMEGA48V-10MI SL383 制造商:Atmel Corporation 功能描述:MCU 8-bit ATmega AVR RISC 4KB Flash 2.5V/3.3V/5V 32-Pin MLF EP T/R
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