參數(shù)資料
型號: ATMEGA645V-8AI
廠商: Atmel
文件頁數(shù): 31/85頁
文件大?。?/td> 0K
描述: IC AVR MCU FLASH 64K 1.8V 64TQFP
產(chǎn)品培訓模塊: megaAVR Introduction
標準包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART,USI
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
PIC16(L)F1824/1828
DS41419C-page 254
Preliminary
2010-2011 Microchip Technology Inc.
25.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSP1 clock is much faster than the system clock.
In Slave mode, when MSSP1 interrupts are enabled,
after the master completes sending data, an MSSP1
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP1 inter-
rupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSP1 interrupt flag bit will be set and if enabled, will
wake the device.
TABLE 25-1:
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
ANSELA
—ANSA4
ANSA2
ANSA1
ANSA0
ANSELB(1)
ANSB7
ANSB6
ANSB5
ANSB4
ANSELC
ANSC7(1)
ANSC6(1)
ANSC3
ANSC2
ANSC1
ANSC0
APFCON0
RXDTSEL
SDOSEL(2)
SSSEL(2)
T1GSEL
TXCKSEL
INLVLA(3)
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
INLVLA(4)
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
INLVLB(1)
INLVLB7
INLVLB6
INLVLB5
INLVLB4
INLVLC(3)
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
INLVLC(4)
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
SSP1BUF
Synchronous Serial Port Receive Buffer/Transmit Register
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSPM<3:0>
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
TRISA(3)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
TRISA(4)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
TRISB(1)
TRISB7
TRISB6
TRISB5
TRISB4
TRISC(3)
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TRISC(4)
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
Legend:
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode.
*
Page provides register information.
Note
1:
PIC16(L)F1828 only.
2:
PIC16(L)F1824 only.
3:
Unshaded cells apply to PIC16(L)F1828 only.
4:
Unshaded cells apply to PIC16(L)F1824 only.
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ATMEGA645V-8AUR 功能描述:8位微控制器 -MCU AVR 64KB FLSH 2KB EE 4KB SRAM-8MHz, IND RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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