參數(shù)資料
型號(hào): ATMEGA645V-8MI
廠商: Atmel
文件頁數(shù): 60/85頁
文件大?。?/td> 0K
描述: IC AVR MCU FLASH 64K 1.8V 64QFN
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 260
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART,USI
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲(chǔ)器容量: 64KB(32K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
35
2570N–AVR–05/11
ATmega325/3250/645/6450
10. Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
10.1
Sleep Modes
F i g u r e 9- 1 on p a g e 26 presents the di f f erent clock systems in the Atmel
ATmega325/3250/645/6450, and their distribution. The figure is helpful in selecting an appropri-
ate sleep mode. Table 10-1 on page 35 shows the different sleep modes and their wake up
sources.
Note:
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT0, only level interrupt.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be
activated by the SLEEP instruction. See Table 10-2 on page 39 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
10.2
Idle Mode
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, USI,
Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode
basically halts clk
CPU and clkFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Table 10-1.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Oscillators
Wake-up Sources
Sleep Mode
clk
CP
U
clk
FLASH
clk
IO
clk
AD
C
clk
AS
Y
Main
Cloc
k
Sour
ce
Enab
led
Ti
mer
O
s
c
Enab
led
IN
T0
an
d
Pi
n
Cha
n
g
e
USI
Star
t
Co
nd
itio
n
Ti
mer
2
SPM
/EEPR
OM
Read
y
ADC
Oth
e
rI
/O
Idle
X
XX
X
ADC Noise
Reduction
X
XX
Power-down
X
Power-save
X
XX
Standby(1)
XX(3)
X
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