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參數(shù)資料
| 型號： | ATMEGA64RZAV-10PU |
| 廠商： | Atmel |
| 文件頁數(shù)： | 18/23頁 |
| 文件大小： | 0K |
| 描述： | MCU ATMEGA644/AT86RF230 40-DIP |
| 產(chǎn)品培訓(xùn)模塊： | MCU Product Line Introduction megaAVR Introduction Introduction to ZigBee Low Power Wireless Networks |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ATMEGA |
| 頻率： | 2.4GHz |
| 調(diào)制或協(xié)議： | 802.15.4 Zigbee |
| 功率 - 輸出： | 3dBm |
| 靈敏度： | -101dBm |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 數(shù)據(jù)接口： | PCB，表面貼裝 |
| 存儲容量： | 64kB 閃存，2kB EEPROM，4kB RAM |
| 天線連接器： | PCB，表面貼裝 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 553 (CN2011-ZH PDF) |
| 配用： | ATSTK600-TQFP32-ND - STK600 SOCKET/ADAPTER 32-TQFP ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM ATSTK500-ND - PROGRAMMER AVR STARTER KIT |
4
2593OS–AVR–02/12
ATmega644
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega644 provides the following features: 64 Kbytes of In-System Programmable Flash
with Read-While-Write capabilities, 2 Kbytes EEPROM, 4 Kbytes SRAM, 32 general purpose I/O
lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible
Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Inter-
face, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain,
programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1
compliant JTAG test interface, also used for accessing the On-chip Debug system and program-
ming and six software selectable power saving modes. The Idle mode stops the CPU while
allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous
timer continues to run, allowing the user to maintain a timer base while the rest of the device is
sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchro-
nous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode,
the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows
very fast start-up combined with low power consumption. In Extended Standby mode, both the
main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega644 is a powerful microcontroller that provides a highly flexible and cost effec-
tive solution to many embedded control applications.
The ATmega644 AVR is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.
2.2
Pin Descriptions
2.2.1
VCC
Digital supply voltage.
2.2.2
GND
Ground.
2.2.3
Port A (PA7:PA0)
Port A serves as analog inputs to the Analog-to-digital Converter.
Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). The Port A output buffers have symmetrical drive characteristics with both high sink
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