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| 型號(hào)： | ATMEL |
| 英文描述： | (426.65 k) |
| 中文描述： | （426.65十一） |
| 文件頁數(shù)： | 17/42頁 |
| 文件大小： | 426K |
| 代理商： | ATMEL |
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Data Book Updates and Changes
17
ATtiny10/11/12
The latest data sheet on the web is rev. 1006B-10/99.
The data sheet in the printed data book is rev. 1006A-04/99.
Changes in the ATtiny10/11/12 Data Sheet on the web:
Page: Change or Add:
27
Table 13: remove this note: “Note: When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its
Interrupt Enable bit in the GIMSK register. Otherwise an interrupt can occur when the bits are changed.”
In the first paragraph of
Sleep modes for the ATtiny10/11
section, replace the sentence
“On wake-up from Power Down Mode on pin change, the two instructions following SLEEP are executed before
the pin change interrupt routine.
by
“On wake-up from Power Down Mode on pin change, 2 instruction cycles are executed before the pin change inter-
rupt flag is updated. During these cycles, the processor executes instructions, but the interrupt condition is not
readable, and the interrupt routine has not started yet.
32
In the note for Table 16, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset
33
In the last sentence of the first paragraph, change “When the EEPROM is read or written, the CPU is halted for two
clock cycles before the next instruction is executed.” to “When the EEPROM is written, the CPU is halted for two
clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock
cycles before the next instruction is executed.”
In the
EEPROM Control Register
description, change the initial value of EEWE from “0” to “X”.
34
In the
Bit 0 - EERE: EEPROM Read Enable
description,
change
“When EERE has been set, the CPU is halted for
two clock cycles before the next instruction is executed.”
to
“When EERE has been set, the CPU is halted for four
clock cycles before the next instruction is executed.”
Changes in the ATtiny10/11/12 section in the data book
Page: Change or Add:
9-3
In both
Pin Configuration
figures, replace RESET with RESET.
9-14
In Figure 12, add a box containing “+1” as an input to the summation operator.
9-24
In the first line of the
Watchdog Reset
section, change “1 XTAL cycle” to “1 CK cycle”.
In Figure 22, change “1 XTAL Cycle” to “1 CK Cycle”.
9-29
Table 13: remove this note: “Note: When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its
Interrupt Enable bit in the GIMSK register. Otherwise an interrupt can occur when the bits are changed.”
In the first paragraph of
Sleep modes for the ATtiny10/11
section, replace the sentence
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