參數(shù)資料
型號: ATSAM3N1BB-AU
廠商: Atmel
文件頁數(shù): 43/60頁
文件大?。?/td> 0K
描述: IC MCU 64KB CORTEX-M3 64-LQFP
標準包裝: 160
系列: SAM3N
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 48MHz
連通性: I²C,IrDA,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 47
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b,D/A 1x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP 裸露焊盤
包裝: 托盤
48
11011BS–ATARM–22-Feb-12
SAM3N Summary
– Two multi-purpose input/output signals
Two global registers that act on all three TC Channels
Quadrature decoder
– Advanced line filtering
– Position/revolution/speed
2-bit Gray Up/Down Counter for Stepper Motor
12.6
Pulse Width Modulation Controller (PWM)
Four channels, one 16-bit counter per channel
Common clock generator, providing thirteen different clocks
– One Modulo n counter providing eleven clocks
– Two independent linear dividers working on modulo n counter outputs
Independent channel programming
– Independent enable/disable commands
– Independent clock selection
– Independent period and duty cycle, with double buffering
– Programmable selection of the output waveform polarity
12.7
10-bit Analog-to-Digital Converter
Up to 16-channel ADC
10-bit 384 Ksamples/sec. or 8-bit 583 Ksamples/sec. Successive Approximation Register
ADC
±2 LSB Integral Non Linearity, ±1 LSB Differential Non Linearity
Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs
External voltage reference for better accuracy on low voltage inputs
Individual enable and disable of each channel
Multiple trigger source
– Hardware or software trigger
– External trigger pin
– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
Sleep Mode and conversion sequencer
– Automatic wakeup on trigger and back to sleep mode after conversions of all
enabled channels
12.8
Digital-to-Analog Converter (DAC)
1 channel 10-bit DAC
Up to 500 ksamples/s conversion rate
Flexible conversion range
Multiple trigger sources
One PDC channel
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