參數(shù)資料
型號: ATSAM3U4EA-CU
廠商: Atmel
文件頁數(shù): 44/60頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 256KB FLSH 144LFBGA
產(chǎn)品培訓模塊: MCU Product Line Introduction
Cortex®-M3 Introduction and Specific SAM3U Implementation
SAM3U Cortex-M3 Based MCU Introduction
Touch Solutions on the Atmel ARM? Cortex?-M3 Based Flash Microcontrollers
標準包裝: 184
系列: SAM3U
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 96MHz
連通性: EBI/EMI,I²C,MMC,SPI,SSC,UART/USART,USB
外圍設備: 欠壓檢測/復位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
RAM 容量: 52K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b,8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LFBGA
包裝: 托盤
配用: ATSAM3U-EK-ND - KIT EVAL FOR AT91SAM3U CORTEX
49
6430FS–ATARM–10-Feb-12
SAM3U Series
– Pulse Generation
–Delay Timing
– Pulse Width Modulation
– Up/Down Capabilities
– Quadrature Decoder Logic
Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
Two global registers that act on all three TC Channels
12.7
Pulse Width Modulation Controller (PWM)
4 channels, one 16-bit counter per channel
Common clock generator, providing Thirteen Different Clocks
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
– High Frequency Asynchronous clocking mode
Independent channel programming
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Independent Output Override for each channel
– Independent complementary Outputs with 12-bit dead time generator for each
channel
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
Synchronous Channel mode
– Synchronous Channels share the same counter
– Mode to update the synchronous channels registers after a programmable number
of periods
Connection to one PDC channel
– Offers Buffer transfer without Processor Intervention, to update duty cycle of
synchronous channels
Two independent event lines which can send up to 8 triggers on ADC within a period
Four programmable Fault Inputs providing asynchronous protection of outputs
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