參數(shù)資料
型號： ATT3030-50M68I
廠商： Electronic Theatre Controls, Inc.
元件分類： FPGA
英文描述： Field-Programmable Gate Arrays
中文描述： 現(xiàn)場可編程門陣列
文件頁數(shù)： 19/80頁
文件大?。?/td> 528K
代理商： ATT3030-50M68I
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Lucent Technologies Inc.
19
Configuration
(continued)
Configuration Data
Configuration data to define the function and interconnection within an FPGA are loaded from an external storage
at powerup and on a reprogram signal. Several methods of automatic and controlled loading of the required data
are available. Logic levels applied to mode selection pins at the start of configuration time determine the method to
be used (see Table 2). The data may be either bit-serial or byte-parallel, depending on the configuration mode.
Various Lucent programmable gate arrays have different sizes and numbers of data frames. For the ATT3020, con-
figuration requires 14779 bits for each device, arranged in 197 data frames. An additional 40 bits are used in the
header (see Figure 20).
* The FPGA devices require four dummy bits minimum.
Figure 19. Internal Configuration Data Structure
11111111
0010
< 24-BIT LENGTH COUNT >
1111
0 < DATA FRAME # 001 > 111
0 < DATA FRAME # 002 > 111
0 < DATA FRAME # 003 > 111
. . .
. . .
. . .
0 < DATA FRAME # 196 > 111
0 < DATA FRAME # 197 > 111
– DUMMY BITS*
– PREAMBLE CODE
– CONFIGURATION PROGRAM LENGTH
– DUMMY BITS (4 BITS MINIMUM)
197 CONFIGURATION DATA FRAMES
(EACH FRAME CONSISTS OF:
A START BIT (0)
A 71-BIT DATA FIELD
THREE STOP BITS
POSTAMBLE CODE (4 BITS MINIMUM)
REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN
1111
FOR ATT3020
HEADER
PROGRAM DATA
)
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