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| 型號(hào)： | ATT3030-50M84I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類(lèi)： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列 |
| 文件頁(yè)數(shù)： | 62/80頁(yè) |
| 文件大小： | 528K |
| 代理商： | ATT3030-50M84I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
62
Lucent Technologies Inc.
Electrical Characteristics
(continued)
* At powerup, V
CC
must rise from 2 V to V
CC
minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding
RESET
low until V
CC
has reached 4 V. A very long V
rise time of >100 ms or a nonmonotonically rising V
CC
may require a >1 μs high level
on
RESET
, followed by a >6 μs low level on
RESET
and DONE/
PROG
after V
CC
has reached 4 V.
Figure 35. General FPGA Switching Characteristics
Testing of the switching characteristics is modeled after testing specified by MIL-M-38510/605. Devices are 100%
functionally tested. Actual worst-case timing is provided by the timing calculator or simulation.
*
RESET
timing relative to valid mode lines (M0, M1, M2) is relevant when
RESET
is used to delay configuration.
PWRDWN
transitions must occur while V
CC
> 4 V.
Table 25. General FPGA Switching Characteristics
Signal
Description
Symbol
Min
Max
Unit
RESET
*
M0, M1, and M2 Setup Time
M0, M1, and M2 Hold Time
RESET
Width (LOW) Required for Abort
T
MR
(2)
T
RM
(3)
T
MRW
(4)
1
4.5
6
—
—
—
μs
μs
μs
DONE/
PROG
Width Low Required for Reconfiguration
INIT
Response After DONE/
PROG
is Pulled Low
T
PGW
(5)
T
PGI
(6)
6
—
—
7
μs
μs
V
CC
Powerdown V
CC (
commercial/industrial)
V
CCPD
2.3
—
V
RESET
M0/M1/M2
DONE/PROG
INIT
(OUTPUT)
T
MRW
PWRDWN
VALID
V
CC
(VALID)
T
MR
T
RM
T
PGW
T
PGI
USER STATE
CONFIGURE
CLEAR STATE
See *
V
CCPD
2
5
3
6
4
5-3124(F)
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