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參數(shù)資料
| 型號： | ATT3030 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 2/80頁 |
| 文件大?。?/td> | 528K |
| 代理商： | ATT3030 |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
2
Lucent Technologies Inc.
Contents
Page
Performance .............................................................29
Device Performance .............................................29
Logic Block Performance ......................................30
Interconnect Performance .....................................30
Power ........................................................................32
Power Distribution .................................................32
Power Dissipation .................................................33
Pin Information .........................................................34
Pin Assignments .......................................................39
Package Thermal Characteristics .............................50
Package Coplanarity .................................................51
Package Parasitics ...................................................51
Absolute Maximum Ratings ......................................53
Electrical Characteristics ..........................................54
Outline Diagrams ......................................................68
Terms and Definitions ...........................................68
44-Pin PLCC .........................................................68
68-Pin PLCC .........................................................69
84-Pin PLCC .........................................................70
100-Pin QFP .........................................................71
100-Pin TQFP .......................................................72
132-Pin PPGA ......................................................73
144-Pin TQFP .......................................................74
160-Pin QFP .........................................................75
175-Pin PPGA ......................................................76
208-Pin SQFP .......................................................77
Ordering Information .................................................78
Contents
Page
Features ..................................................................... 1
Description ................................................................. 1
Architecture ................................................................ 3
Configuration Memory................................................ 4
I/O Block ..................................................................... 5
Summary of I/O Options ......................................... 6
Configurable Logic Block ............................................7
Programmable Interconnect ....................................... 9
General-Purpose Interconnect ............................. 10
Direct Interconnect ............................................... 11
Long Lines ............................................................ 13
Internal Buses ...................................................... 14
Crystal Oscillator .................................................. 16
Configuration ............................................................ 17
Initialization Phase ............................................... 17
Configuration Data ............................................... 19
Configuration Modes ................................................ 22
Master Mode ........................................................ 22
Peripheral Mode ................................................... 24
Slave Mode .......................................................... 25
Daisy Chain .......................................................... 26
Special Configuration Functions .............................. 27
Input Thresholds ................................................... 27
Readback ............................................................. 27
Reprogram ........................................................... 28
DONE Pull-Up ...................................................... 28
DONE Timing ....................................................... 28
RESET Timing ...................................................... 28
Crystal Oscillator Division .................................... 28
Table of Contents
相關PDF資料 |
PDF描述 |
|---|---|
| ATT3030-100H132I | Field-Programmable Gate Arrays |
| ATT3030-100H44I | Field-Programmable Gate Arrays |
| ATT3030-100H68I | Field-Programmable Gate Arrays |
| ATT3030-100H84I | Field-Programmable Gate Arrays |
| ATT3030-100J132I | Field-Programmable Gate Arrays |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ATT3030-100H132I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3030-100H44I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3030-100H68I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3030-100H84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3030-100J100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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