參數(shù)資料
型號: ATTINY13A-SSU
廠商: Atmel
文件頁數(shù): 53/67頁
文件大?。?/td> 0K
描述: IC MCU AVR 1K FLASH 20MHZ 8SOIC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 100
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 6
程序存儲器容量: 1KB(512 x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 612 (CN2011-ZH PDF)
配用: ATSTK600-DIP40-ND - STK600 SOCKET/ADAPTER 40-PDIP
ATAVRDRAGON-ND - KIT DRAGON FLASH MEM AVR
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATJTAGICE2-ND - AVR ON-CHIP D-BUG SYSTEM
33
8126F–AVR–05/12
ATtiny13A
7.4.6
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
both the I/O clock (clk
I/O) and the ADC clock (clkADC) are stopped, the input buffers of the device
will be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 53 for details on
which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an
analog signal level close to V
CC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
CC/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to
7.5
Register Description
7.5.1
BODCR – Brown-Out Detector Control Register
The BOD Control Register contains control bits for disabling the BOD by software.
Bit 1 – BODS: BOD Sleep
In order to disable BOD during sleep the BODS bit must be written to logic one. This is controlled
by a timed sequence and the enable bit, BODSE. First, both BODS and BODSE must be set to
one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to
zero. The BODS bit is active three clock cycles after it is set. A sleep instruction must be exe-
cuted while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit
is automatically cleared after three clock cycles.
Bit 0 – BODSE: BOD Sleep Enable
The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD
disable is controlled by a timed sequence.
7.5.2
MCUCR – MCU Control Register
The MCU Control Register contains control bits for power management.
Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
Bit
7
654
32
10
BODS
BODSE
BODCR
Read/Write
RR
R/W
Initial Value
0
Bit
7
654
32
10
PUD
SE
SM1
SM0
ISC01
ISC00
MCUCR
Read/Write
R
R/W
R
R/W
Initial Value
0
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