參數(shù)資料
型號: ATTINY24A-CCU
廠商: Atmel
文件頁數(shù): 40/135頁
文件大小: 0K
描述: MCU AVR 2KB FLASH 20MHZ 15-UFBGA
產(chǎn)品培訓模塊: MCU Product Line Introduction
tinyAVR Introduction
標準包裝: 490
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: USI
外圍設備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 2KB(1K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 15-UFBGA
包裝: 托盤
134
32015G–AVR32–09/09
AT32AP7001
15.4.2
Power Management
Edge triggered interrupts are available in all sleep modes except Deepdown. Level triggered
interrupts and the NMI interrupt are available in all sleep modes.
15.4.3
Interrupt
The EIC interrupt lines are connected to internal sources of the interrupt controller. Using the
External Interrutps requires the interrupt controller to be programmed first.
Using the Non-Maskable Interrupt does not require the interrupt controller to be programmed.
15.5
Functional Description
15.5.1
External Interrupts
Each external interrupt pin EXTINTn can be configured to produce an interrupt on rising or fall-
ing edge, or high or low level. External interrupts are configured by the MODE, EDGE, and
LEVEL registers. Each interrupt n has a bit INTn in each of these registers.
Similarly, each interrupt has a corresponding bit in each of the interrupt control and status regis-
ters. Writing 1 to the INTn strobe in IER enables the external interrupt on pin EXTINTn, while
writing 1 to INTn in IDR disables the external interrupt. IMR can be read to check which inter-
rupts are enabled. When the interrupt triggers, the corresponding bit in ISR will be set. For edge
triggered interrupts, the flag remains set until the corresponding strobe bit in ICR is written to 1.
For level triggered interrupts, the flag remains set for as long as the interrupt condition is present
on the pin.
Writing INTn in MODE to 0 enables edge triggered interrupts, while writing the bit to 1 enables
level triggered interrupts.
If EXTINTn is configured as an edge triggered interrupt, writing INTn in EDGE to 0 will trigger the
interrupt on falling edge, while writing the bit to 1 will trigger the interrupt on rising edge.
If EXTINTn is configured as a level triggered interrupt, writing INTn in LEVEL to 0 will trigger the
interrupt on low level, while writing the bit to 1 will trigger the interrupt on high level.
15.5.1.1
Synchronization of external interrupts
The pin value of the EXTINTn pins is normally synchronized to the CPU clock, so spikes shorter
than a CPU clock cycle are not guaranteed to produce an interrupt. In Stop mode, spikes shorter
than a 32KHz clock cycle are not guaranteed to produce an interrupt. In Deepdown mode, only
unsynchronized level interrupts remain active, and any short spike on this interrupt will wake up
the device.
15.5.2
NMI Control
The Non-Maskable Interrupt of the CPU is connected to the NMI_N pin through masking logic in
the External Interrupt Controller. This masking ensures that the NMI will not trigger before the
CPU has been set up to handle interrupts. Writing the EN bit in the NMIC register enables the
NMI interrupt, while writing EN to 0 disables the NMI interrupt. When enabled, the interrupt trig-
gers whenever the NMI_N pin is negated.
The NMI_N pin is synchronized the same way as external level interrupts.
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