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| 型號(hào)： | ATTINY24A-MU |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 133/135頁(yè) |
| 文件大小： | 0K |
| 描述： | MCU AVR 2KB FLASH 20MHZ 20QFN |
| 產(chǎn)品培訓(xùn)模塊： | MCU Product Line Introduction tinyAVR Introduction |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | AVR® ATtiny |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | USI |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲(chǔ)器容量： | 2KB（1K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| EEPROM 大?。?/td> | 128 x 8 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-WFQFN 裸露焊盤(pán) |
| 包裝： | 托盤(pán) |
| 配用： | ATSTK505-ND - ADAPTER KIT FOR 14PIN AVR MCU |
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97
32015G–AVR32–09/09
AT32AP7001
11.5.4.1
Selecting PLL or oscillator for the main clock
The common main clock can be connected to Oscillator 0 or PLL0. By default, the main clock will
be connected to the Oscillator 0 output. The user can connect the main clock to the PLL0 output
by writing the PLLSEL bit in the Main Clock Control Register (MCCTRL) to 1. This must only be
done after PLL0 has been enabled, otherwise a deadlock will occur. Care should also be taken
that the new frequency of the synchronous clocks does not exceed the maximum frequency for
each clock domain.
11.5.4.2
Selecting synchronous clock division ratio
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.
By default, the synchronous clocks run on the undivided main clock. The user can select a pres-
caler division for the CPU clock by writing CKSEL:CPUDIV to 1 and CPUSEL to the prescaling
value, resulting in a CPU clock frequency:
f
CPU = fmain / 2
(CPUSEL+1)
Similarly, the clock for HSB, PBA, and PBB can be divided by writing their respective bitfields.
To ensure correct operation, frequencies must be selected so that f
CPU
f
HSB
f
PBA,B. Also, fre-
quencies must never exceed the specified maximum frequency for each clock domain.
CKSEL can be written without halting or disabling peripheral modules. Writing CKSEL allows a
new clock setting to be written to all synchronous clocks at the same time. It is possible to keep
one or more clocks unchanged by writing the same value a before to the xxxDIV and xxxSEL bit-
fields. This way, it is possible to e.g. scale CPU and HSB speed according to the required
performance, while keeping the PBA and PBB frequency constant.
11.5.4.3
Clock Ready flag
There is a slight delay from CKSEL is written and the new clock setting becomes effective. Dur-
ing this interval, the Clock Ready (CKRDY) flag in ISR will read as 0. If IER:CKRDY is written to
1, the Power Manager interrupt can be triggered when the new clock setting is effective. CKSEL
must not be re-written while CKRDY is 0, or the system may become unstable or hang.
11.5.5
Peripheral clock masking
By default, the clock for all modules are enabled, regardless of which modules are actually being
used. It is possible to disable the clock for a module in the CPU, HSB, PBA, or PBB clock
domain by writing the corresponding bit in the Clock Mask register (CPU/HSB/PBA/PBB) to 0.
When a module is not clocked, it will cease operation, and its registers cannot be read or written.
The module can be re-enabled later by writing the corresponding mask bit to 1.
A module may be connected to several clock domains, in which case it will have several mask
bits.
Table 11-1 contains a list of implemented maskable clocks.
11.5.5.1
Cautionary note
Note that clocks should only be switched off if it is certain that the module will not be used.
Switching off the clock for the internal RAM will cause a problem if the stack is mapped there.
Switching off the clock to the Power Manager (PM), which contains the mask registers, or the
corresponding PB bridge, will make it impossible to write the mask registers again. In this case,
they can only be re-enabled by a system reset.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ATTINY24A-MUR | 功能描述:8位微控制器 -MCU AVR 2KB FLSH 128B EE USI ADC 20MHz, IND RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ATTINY24A-PU | 功能描述:8位微控制器 -MCU 20MHz, 1.8-5.5V Industrial Temp RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ATTINY24A-SSF | 功能描述:8位微控制器 -MCU 2KB FL 128B EE SRAM USIADC 20MHz Hi+125C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ATTINY24A-SSFR | 功能描述:8位微控制器 -MCU 2KB FL 128B EE SRAM USIADC 20MHz Hi+125C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ATTINY24A-SSN | 功能描述:8位微控制器 -MCU 2K FLASH 128B EE 128B SRAM USI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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