參數(shù)資料
型號: ATTINY24A-SSUR
廠商: Atmel
文件頁數(shù): 54/135頁
文件大?。?/td> 0K
描述: MCU AVR 2KB FLASH 20MHZ 14SOIC
產(chǎn)品培訓模塊: MCU Product Line Introduction
tinyAVR Introduction
標準包裝: 1
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: USI
外圍設(shè)備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 2KB(1K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 標準包裝
其它名稱: ATTINY24A-SSURDKR
24
8183F–AVR–06/12
ATtiny24A/44A/84A
6.
Clock System
Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in “Power Manage-
Figure 6-1.
Clock Distribution
6.1
Clock Subsystems
The clock subsystems are detailed in the sections below.
6.1.1
CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
General I/O
Modules
CPU Core
RAM
clk
I/O
AVR Clock
Control Unit
clk
CPU
Flash and
EEPROM
clk
FLASH
Source clock
Watchdog Timer
Watchdog
Oscillator
Reset Logic
Clock
Multiplexer
Watchdog clock
Calibrated RC
Oscillator
Calibrated RC
Oscillator
External Clock
ADC
clk
ADC
Crystal
Oscillator
Low-Frequency
Crystal Oscillator
System Clock
Prescaler
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