參數(shù)資料
型號: ATTINY4313-PU
廠商: Atmel
文件頁數(shù): 13/22頁
文件大?。?/td> 0K
描述: IC MCU AVR 4K FLASH 20PDIP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 18
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
配用: ATSTK600-SC01-ND - STK600 DIP SOCKET CARD AVR
PIC16F872
DS30221C-page 18
2006 Microchip Technology Inc.
2.2.2.7
PIR2 Register
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.
.
REGISTER 2-7:
PIR2 REGISTER (ADDRESS: 0Dh)
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0
R/W-0
U-0
R/W-0
U-0
R/W-0
reserved
EEIF
BCLIF
reserved
bit 7
bit 0
bit 7
Unimplemented: Read as '0'
bit 6
Reserved: Always maintain this bit clear
bit 5
Unimplemented: Read as '0'
bit 4
EEIF: EEPROM Write Operation Interrupt Flag bit
1
= The write operation completed (must be cleared in software)
0
= The write operation is not complete or has not been started
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1
= A bus collision has occurred in the SSP, when configured for I2C Master mode
0
= No bus collision has occurred
bit 2-1
Unimplemented: Read as '0'
bit 0
Reserved: Always maintain this bit clear
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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