參數(shù)資料
型號: ATTINY43U-MUR
廠商: Atmel
文件頁數(shù): 147/158頁
文件大小: 0K
描述: MCU AVR 4KB FLASH 8MHZ 20QFN
產(chǎn)品培訓模塊: tinyAVR Introduction
標準包裝: 6,000
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: USI
外圍設備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-WFQFN 裸露焊盤
包裝: 帶卷 (TR)
89
8048C–AVR–02/12
ATtiny43U
Figure 12-7. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OCnx pins. Setting the COMnx[1:0] bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COMnx[1:0] to three: Setting the COMnA0 bits to
one allows the OCnA pin to toggle on Compare Matches if the WGMn2 bit is set. This option is
not available for the OCnB pin (See Table 12-4 on page 93). The actual OCnx value will only be
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OCnx Register at the Compare Match between OCRnx
and TCNTn when the counter increments, and setting (or clearing) the OCnx Register at Com-
pare Match between OCRnx and TCNTn when the counter decrements. The PWM frequency for
the output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCRnA Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnA is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 12-7 on page 89 OCn has a transition from high to low
even though there is no Compare Match. The point of this transition is to guaratee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1
2
3
TCNTn
Period
OCn
(COMnx[1:0] = 2)
(COMnx[1:0] = 3)
OCRnx Update
f
OCnxPCPWM
fclk_I/O
N 510
------------------
=
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