參數(shù)資料
型號： ATTINY43U-SUR
廠商： Atmel
文件頁數(shù)： 107/158頁
文件大?。?/td> 0K
描述： MCU AVR 4KB FLASH 8MHZ 20SOIC
產(chǎn)品培訓(xùn)模塊： tinyAVR Introduction
標(biāo)準(zhǔn)包裝： 1,000
系列： AVR® ATtiny
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： USI
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 16
程序存儲器容量： 4KB（2K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
包裝： 帶卷 (TR)
其它名稱： ATTINY43U-SUR-ND
52
8048C–AVR–02/12
ATtiny43U
9.2.4
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
TOUT. See
“Watchdog Timer” on page 52 for details on operation of the Watchdog Timer.
Figure 9-6.
Watchdog Reset During Operation
9.3
Internal Voltage Reference
ATtiny43U features an internal bandgap reference. This reference is used for Brown-out Detec-
tion, and it can be used as an input to the Analog Comparator or the ADC.
9.3.1
Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in Table 20-4 on page 161. To save power, the reference is not always
turned on. The reference is on during the following situations:
1.
When the BOD is enabled (by programming the BODLEVEL[2..0] Fuse).
2.
When the bandgap reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR).
3.
When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
9.4
Watchdog Timer
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling
the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table
9-3 on page 57. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The
Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different
clock cycle periods can be selected to determine the reset period. If the reset period expires
without another Watchdog Reset, the ATtiny43U resets and executes from the Reset Vector.
For timing details on the Watchdog Reset, refer to Table 9-3 on page 57.
CK
CC
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ATTINY441-MMHR 制造商:Atmel Corporation 功能描述:16MHZ,3X3MM, 20VQFN, IND.GRADE,GREEN T&R - Tape and Reel 制造商:Atmel Corporation 功能描述:IC MCU 8BIT 4KB FLASH 20VQFN
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