參數(shù)資料
型號： ATTINY44A-PU
廠商： Atmel
文件頁數(shù)： 33/135頁
文件大?。?/td> 0K
描述： IC MCU AVR 4K FLASH 20MHZ 14PDIP
產(chǎn)品培訓模塊： MCU Product Line Introduction
tinyAVR Introduction
標準包裝： 25
系列： AVR® ATtiny
核心處理器： AVR
芯體尺寸： 8-位
速度： 20MHz
連通性： USI
外圍設備： 欠壓檢測/復位，POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 12
程序存儲器容量： 4KB（2K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 14-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁面： 613 (CN2011-ZH PDF)
配用： ATSTK600-RC12-ND - STK600 ROUTING CARD AVR
ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
128
32015G–AVR32–09/09
AT32AP7001
Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status
register, namely Interrupt Level 3 Mask (I3M) to Interrupt Level 0 Mask (I0M), and Global Inter-
rupt Mask (GM). An interrupt request is masked if either the GM or the corresponding interrupt
level mask bit is set.
The Prioritizer hardware uses the ValReq lines and the INTLEVEL field in the IPRs to select the
pending interrupt of the highest priority. If an NMI interrupt request is pending, it automatically
gets the highest priority of any pending interrupt. If several interrupt groups of the highest pend-
ing interrupt level have pending interrupts, the interrupt group with the highest number is
selected.
The INTLEVEL and handler autovector offset (AUTOVECTOR) of the selected interrupt are
transmitted to the CPU for interrupt handling and context switching. The CPU does not need to
know which interrupt is requesting handling, but only the level and the offset of the handler
address. The IRR registers contain the interrupt request lines of the groups and can be read via
user interface registers for checking which interrupts of the group are actually active.
14.5.1
Non-Maskable Interrupts
A NMI request has priority over all other interrupt requests. NMI has a dedicated exception vec-
tor address defined by the AVR32 architecture, so AUTOVECTOR is undefined when
INTLEVEL indicates that an NMI is pending.
14.5.2
CPU Response
When the CPU receives an interrupt request it checks if any other exceptions are pending. If no
exceptions of higher priority are pending, interrupt handling is initiated. When initiating interrupt
handling, the corresponding interrupt mask bit is set automatically for this and lower levels in sta-
tus register. E.g, if an interrupt of level 3 is approved for handling, the interrupt mask bits I3M,
I2M, I1M, and I0M are set in status register. If an interrupt of level 1 is approved, the masking
bits I1M and I0M are set in status register. The handler address is calculated by adding
AUTOVECTOR to the CPU system register Exception Vector Base Address (EVBA). The CPU
will then jump to the calculated address and start executing the interrupt handler.
Setting the interrupt mask bits prevents the interrupts from the same and lower levels to be
passed through the interrupt controller. Setting of the same level mask bit prevents also multiple
requests of the same interrupt to happen.
It is the responsibility of the handler software to clear the interrupt request that caused the inter-
rupt before returning from the interrupt handler. If the conditions that caused the interrupt are not
cleared, the interrupt request remains active.
14.5.3
Clearing an Interrupt Request
Clearing of the interrupt request is done by writing to registers in the corresponding peripheral
module, which then clears the corresponding NMIREQ/IREQ signal.
The recommended way of clearing an interrupt request is a store operation to the controlling
peripheral register, followed by a dummy load operation from the same register. This causes a
pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is
exited and the interrupt mask is cleared before the interrupt request is cleared.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ATTINY44A-SSF 功能描述:8位微控制器 -MCU 4KB FL 256B EE 256B SRAM 20MHz Hi +125C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
ATTINY44A-SSFR 功能描述:8位微控制器 -MCU 4KB FL 256B EE 256B SRAM 20MHz Hi +125C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
ATTINY44A-SSN 功能描述:8位微控制器 -MCU 4K FLASH 256B EE 256B SRAM - 20MHz RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
ATTINY44A-SSNR 功能描述:8位微控制器 -MCU AVR 4KB FL 256B EE 256B SRAM 20MHz 105C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
ATTINY44A-SSU 功能描述:8位微控制器 -MCU 1.8V, 20MHz Industrial Temp RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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