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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ATUC128D4-AUR
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 557/755闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 128KB FLASH 48TQFP
妯欐簴鍖呰锛� 2,500
绯诲垪锛� AVR®32 UC3 D
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 32-浣�
閫熷害锛� 48MHz
閫i€氭€э細 I²C锛孲PI锛孶ART/USART锛孶SB
澶栧湇瑷倷锛� 娆犲妾㈡脯/寰╀綅锛孌MA锛孖²S锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 35
绋嬪簭瀛樺劜鍣ㄥ閲忥細 128KB锛�128K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 16K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.65 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 6x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 48-TQFP
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� ATUC128D4-AUR-ND
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60
32133D鈥�11/2011
UC3D
9. HSB Bus Matrix (HMATRIXB)
Rev: 1.3.0.3
9.1
Features
User Interface on peripheral bus
Configurable number of masters (up to 16)
Configurable number of slaves (up to 16)
One decoder for each master
Programmable arbitration for each slave
鈥� Round-Robin
鈥� Fixed priority
Programmable default master for each slave
鈥� No default master
鈥� Last accessed default master
鈥� Fixed default master
One cycle latency for the first access of a burst
Zero cycle latency for default master
One special function register for each slave (not dedicated)
9.2
Overview
The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths
between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the
overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to up to 16 HSB Slaves.
The normal latency to connect a master to a slave is one cycle except for the default master of
the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16
Special Function Registers (SFR) that allow the Bus Matrix to support application specific
features.
9.3
Product Dependencies
In order to configure this module by accessing the user registers, other parts of the system must
be configured correctly, as described below.
9.3.1
Clocks
The clock for the HMATRIX bus interface (CLK_HMATRIX) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager.
9.4
Functional Description
9.4.1
Special Bus Granting Mechanism
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This mechanism reduces latency at first access of a burst or single
transfer. This bus granting mechanism sets a different default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to
its associated default master. A slave can be associated with three kinds of default masters: no
default master, last access master, and fixed default master.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-B72-IW-F2 CONVERTER MOD DC/DC 15V 100W
V24C12H150B2 CONVERTER MOD DC/DC 12V 150W
VI-B71-IX-F3 CONVERTER MOD DC/DC 12V 75W
VI-B71-IX-F2 CONVERTER MOD DC/DC 12V 75W
VI-B71-IX-F1 CONVERTER MOD DC/DC 12V 75W
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鍙冩暩(sh霉)鎻忚堪
ATUC128D4-AUT 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3D4 128KB FL 85C RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT
ATUC128D4-Z1UR 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3D4 128KB FL 85C RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT
ATUC128D4-Z1UT 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3D4 128KB FL 85C RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT
ATUC128L3U-AUR 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3L-128KB Flash 64QFP 85C green T&R RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT
ATUC128L3U-AUT 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3L-128KB Flash 64QFP 85C green TRAY RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT