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參數(shù)資料
| 型號： | ATV2500B-15KC |
| 廠商： | Atmel |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 15NS CERAMIC 44JLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | ATV2500B(L) 和 BQ(L) |
| 可編程類型： | UV 可擦除 |
| 最大延遲時間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 宏單元數(shù)： | 24 |
| 輸入/輸出數(shù)： | 24 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.58x16.58） |
| 包裝： | 管件 |
| 其它名稱： | ATV2500B15KC |
ATV2500B(Q)(L)
11
Power-up Reset
The registers in the ATV2500Bs are designed to reset dur-
ing power-up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. The output
state will depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1.
The VCC rise must be monotonic,
2.
After reset occurs, all input and feedback setup
times must be met before driving the clock pin or
terms high, and
3.
The clock pin, and any signals from which clock
terms are derived, must remain stable during tPR.
.
Level Forced on
Odd I/O Pin
during
PRELOAD Cycle
Q Select Pin
State
Even/Odd Select
Even Q1 State
after Cycle
Even Q2 State
after Cycle
Odd Q1 State
after Cycle
Odd Q2 State
after Cycle
V
IH/VIL
Low
High/Low
X
VIH/VIL
High
Low
X
High/Low
X
V
IH/VIL
Low
High
X
High/Low
X
V
IH/VIL
High
X
High/Low
Parameter
Description
Typ
Max
Units
t
PR
Power-up Reset Time
600
1000
ns
VRST
Power-up Reset Voltage
3.8
4.5
V
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