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參數(shù)資料
| 型號： | AV2636 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 24-bit 192kHz Stereo Audio DAC |
| 中文描述： | 24位192kHz立體聲音頻DAC |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 821K |
| 代理商： | AV2636 |
AV2636
Product Datasheet
SERIAL CONTROL INTERFACE
The AV2636 supports a 2-wire I
2
C compatible serial control interface. When MODE pin is externally
pulled high, the FMTC and FMTD pins function as SCL and SDA. Where SCL is serial clock input and
SDA is serial data input and output. The internal control registers can be programmed through the
interface.
The chip ID for the AV2636 is a 7-bit hexadecimal number “32hex”. The protocol for write operation
consists of sending 3 bytes of data to the AV2636 at SDA pin. Following each byte is the acknowledge bit
generated by the AV2636. The first byte is the 7-bit chip ID followed by the read/write bit (read is logic
high and write is logic low). The second byte is control register address. The third byte is control register
data. The following diagram shows a “write” sequence and timing of control register address 00H and
data 30H.
SDA
SCL
START CA6 CA0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP
0
1
1
0
0
1
1
Chip ID: CA[6:0] = 0110010
Register Address: A[7:0] = 00H
Data: D[7:0] = 30H
Timing specifications
t
BF
STOP
START
STOP
t
DH_STA
t
LOW
t
r
t
f
t
HIGH
t
DH_DA
t
DS_DA
t
DS_STO
START
t
DS_STA
SDA
SCL
Symbol
f
SC
t
DS_STA
t
DH_STA
t
DS_STO
t
LOW
t
HIGH
tr
tf
t
DS_DA
t
DH_DA
t
BF
Descriptions
Min
4.7
4.0
4.0
4.7
4.0
250
0
4.7
Max
100
1.0
0.3
Units
kHz
μs
μs
μs
μs
μs
μs
μs
ns
ns
μs
SCL clock frequency
START condition SDA setup time
START condition SDA hold time
STOP condition SDA setup time
SCL low pulse time
SCL high pulse time
SCL and SDA rise time
SCL and SDA fall time
Data setup time
Data hold time
Bus free time
AVS Technology, Inc.
www.avstech.com
9-16
August 18, 2004
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