![](http://datasheet.mmic.net.cn/90000/MC80C32E-12-883-D_datasheet_2371307/MC80C32E-12-883-D_71.png)
71
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15..8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
13.2.9
PCMSK0 – Pin Change Mask Register 0
Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7..0
Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the cor-
responding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Bit
7
65
43
21
0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
PCMSK0
Read/Write
R/W
Initial Value
0