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參數(shù)資料
| 型號(hào)： | AV9172-01CN16 |
| 英文描述： | Direct mounting on the PCB, Crimping connection, Discrete wire connectors; HRS No: 544-0003-4 00; No. of Positions: 2; Connector Type: Wire; Contact Gender: Male; Contact Spacing (mm): 2; Terminal Pitch (mm): 2; Current Rating(Amps)(Max.): 3; Operating Temperature Range (degrees C): -30 to 85; General Description: Plug; Crimping; Direct PCB mounting; Single row |
| 中文描述： | 低偏移輸出緩沖 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 399K |
| 代理商： | AV9172-01CN16 |
4
AV9172
Pin Configuration
Functionality Table for AV9172-03
CLKIN Input Frequency=X, input range is 10 to 50 MHz.
Example Table for AV9172-03
(33 MHz input, all frequencies in MHz.)
Timing Diagram for AV9172-03
16-Pin SOIC or 16-Pin PDIP
Note: The phase alignment between the 1X clock outputs and
reference clocks input will be either at a 0 or 180 degrees
offset if the 2X clock is used as the feedback signal (con-
nected to the FBIN pin). Which relationship occurs is totally
random and has the potential to change any time the device has
its VDD supply cycled off or the devices input clock
removed.
EN2
0
1
0
1
INV#
0
0
1
1
Q0
2X
2X
2X
2X
Q1
2X
2X
2X
2X
Q2
2X
2X
2X
2X
Q3
2X
2X
1X
1X
Q4
2X
2X
1X
1X
Q5
2X
1X
2X
1X
EN2
0
1
0
1
INV#
0
0
1
1
Q0
66
66
66
66
Q1
66
66
66
66
Q2
66
66
66
66
Q3
66
66
33
33
Q4
66
66
33
33
Q5
66
33
66
33
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AV9173-01CN08 | Video Genlock PLL |
| AV9173-01 | Video Genlock PLL |
| AV9173-01CS08 | Video Genlock PLL |
| AVA-0005S | Delay Line |
| AVA-0010 | Delay Line |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AV9172-01CS16 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Skew Output Buffer |
| AV9172-01CW16 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Skew Output Buffer |
| AV9172-03 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Skew Output Buffer |
| AV9172-03CC16 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Skew Output Buffer |
| AV9172-03CN16 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Skew Output Buffer |
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