參數(shù)資料
型號(hào): AX1000-1FG484I
元件分類: FPGA
英文描述: FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA484
封裝: 1 MM PITCH, FBGA-484
文件頁(yè)數(shù): 189/230頁(yè)
文件大?。?/td> 6485K
代理商: AX1000-1FG484I
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Axcelerator Family FPGAs
v2.8
2-47
R-Cell
Introduction
The
R-cell,
the
sequential
logic
resource
of
the
Axcelerator devices, is the second logic module type in
the AX family architecture. It includes clock inputs for all
eight global resources of the Axcelerator architecture as
well as global presets and clears (Figure 2-31).
The main features of the R-cell include the following:
Direct connection to the adjacent logic module
through the hardwired connection DCIN. DCIN is
driven by the DCOUT of an adjacent C-cell via the
Direct-Connect routing resource, providing a
connection with less than 0.1 ns of routing delay.
The R-cell can be used as a standalone flip-flop. It
can be driven by any C-cell or I/O modules through
the regular routing structure (using DIN as a
routable data input). This gives the option of
using the R-Cell as a 2:1 MUXed flip-flop as well.
Provision of data enable-input (S0).
Independent active-low asynchronous clear (CLR).
Independent
active-low
asynchronous
preset
(PSET). If both CLR and PSET are low, CLR has
higher priority.
Clock can be driven by any of the following (CKP
selects clock polarity):
One of the four high performance hardwired
fast clocks (HCLKs)
One of the four routed clocks (CLKs)
User signals
Global power-on clear (GCLR) and preset (GPSET),
which drive each flip-flop on a chip-wide basis.
When the Global Set Fuse option in the
Designer software is unchecked (by default),
GCLR = 0 and GPSET =1 at device power-up.
When the option is checked, GCLR = 1 and
GPSET= 0. Both pins are pulled High when the
device is in user mode.
S0, S1, PSET, and CLR can be driven by routed
clocks CLKE/F/G/H or user signals.
DIN and S1 can be driven by user signals.
As with the C-cell, the configuration of the R-cell to
perform various functions is handled automatically for
the user through Actel's extensive macro library (please
see Actel’s Antifuse Macro Library Guide for a complete
listing of available AX macros).
Figure 2-31 R-Cell
S1
S0
CKP
CLR
GCLR
PSET
GPSET
DCIN
DIN(user signals)
CKS
Y
HCLKA/B/C/D
CLKE/F/G/H
Internal Logic
相關(guān)PDF資料
PDF描述
AX1000-1FG484MX79 FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA484
AX1000-1FG484M FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA484
AX1000-1FG484X79 FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA484
AX1000-1FG484 FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA484
AX1000-1FG676IX79 FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA676
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AX1000-1FG484M 制造商:Microsemi Corporation 功能描述:FPGA Axcelerator Family 612K Gates 12096 Cells 763MHz 0.15um Technology 1.5V 484-Pin FBGA 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 612K GATES 12096 CELLS 763MHZ 0.15UM 1.5V 4 - Trays
AX1000-1FG676 功能描述:IC FPGA AXCELERATOR 1M 676-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA(23x23)
AX1000-1FG676I 功能描述:IC FPGA AXCELERATOR 1M 676-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA(23x23)
AX1000-1FG676M 制造商:Microsemi Corporation 功能描述:FPGA Axcelerator Family 612K Gates 12096 Cells 763MHz 0.15um Technology 1.5V 676-Pin FBGA 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 612K GATES 12096 CELLS 763MHZ 0.15UM 1.5V 6 - Trays
AX1000-1FG896 功能描述:IC FPGA AXCELERATOR 1M 896-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA(23x23)