參數(shù)資料
型號: AX1000-1FGG484I
元件分類: FPGA
英文描述: FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA484
封裝: 1 MM PITCH, FBGA-484
文件頁數(shù): 24/230頁
文件大?。?/td> 6485K
代理商: AX1000-1FGG484I
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Axcelerator Family FPGAs
1- 6
v2.8
operating with input frequencies ranging from 14 MHz
to 200 MHz and can generate output frequencies
between 20 MHz and 1 GHz. The clock can be either
divided or multiplied by factors ranging from 1 to 64.
Additionally, multiply and divide settings can be used in
any combination as long as the resulting clock frequency
is between 20 MHz and 1 GHz. Adjacent PLLs can be
cascaded to create complex frequency combinations.
The PLL can be used to introduce either a positive or a
negative clock delay of up to 3.75 ns in 250 ps
increments. The reference clock required to drive the PLL
can be derived from three sources: external input pad
(either single-ended or differential), internal logic, or the
output of an adjacent PLL.
Low Power (LP) Mode
The AX architecture was created for high-performance
designs but also includes a low power mode (activated via
the LP pin). When the low power mode is activated, I/O
banks can be disabled (inputs disabled, outputs tristated),
and PLLs can be placed in a power-down mode. All
internal register states are maintained in this mode.
Furthermore, individual I/O banks can be configured to
opt out of the LP mode, thereby giving the designer access
to critical signals while the rest of the chip is in low power
mode.
The power can be further reduced by providing an
external voltage source (VPUMP) to the device to bypass
the internal charge pump (See "Low Power Mode" on
page 2-89 for more information).
Design Environment
The Axcelerator family of FPGAs is fully supported by both
Actel's Libero Integrated Design Environment and
Designer FPGA Development software. Actel Libero IDE is
an integrated design manager that seamlessly integrates
design tools while guiding the user through the design
flow, managing all design and log files, and passing
necessary design data among tools. Additionally, Libero
IDE allows users to integrate both schematic and HDL
synthesis into a single flow and verify the entire design in
a single environment (see the Libero IDE Flow diagram
located on Actel’s website). Libero IDE includes Synplify
Actel Edition (AE) from Synplicity, ViewDraw AE from
Mentor Graphics, ModelSim HDL Simulator from
Mentor
Graphics,
WaveFormer
Lite
AE
from
SynaptiCAD, and Designer software from Actel.
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
the following:
Timer – a world-class integrated static timing analyzer
and constraints editor which support timing-driven
place-and-route
NetlistViewer – a design netlist schematic viewer
ChipPlanner – a graphical floorplanner viewer and editor
SmartPower – allows the designer to quickly estimate
the power consumption of a design
PinEditor – a graphical application for editing pin
assignments and I/O attributes
I/O Attribute Editor – displays all assigned and
unassigned I/O macros and their attributes in a
spreadsheet format
Figure 1-8 AX Routing Structures
相關(guān)PDF資料
PDF描述
AX1000-1FGG484M FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA484
AX1000-1FGG484 FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA484
AX1000-1FGG676I FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA676
AX1000-1FGG676M FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA676
AX1000-1FGG676 FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA676
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AX1000-1FGG484M 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 612K GATES 12096 CELLS 763MHZ 0.15UM 1.5V 4 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 317 I/O 484FBGA
AX1000-1FGG676 功能描述:IC FPGA AXCELERATOR 1M 676-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA(23x23)
AX1000-1FGG676I 功能描述:IC FPGA AXCELERATOR 1M 676-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA(23x23)
AX1000-1FGG676M 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 612K GATES 12096 CELLS 763MHZ 0.15UM 1.5V 6 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA AXCELERATOR 1M 676FBGA 制造商:Microsemi Corporation 功能描述:IC FPGA 418 I/O 676FBGA
AX1000-1FGG896 功能描述:IC FPGA AXCELERATOR 1M 896-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA(23x23)