參數(shù)資料
型號(hào): AX1000-1FGG896
元件分類: FPGA
英文描述: FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA896
封裝: 1 MM PITCH, FBGA-896
文件頁(yè)數(shù): 209/230頁(yè)
文件大?。?/td> 6485K
代理商: AX1000-1FGG896
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Axcelerator Family FPGAs
1- 2
v2.8
Logic Modules
Actel's Axcelerator family provides two types of logic
modules: the register cell (R-cell) and the combinatorial
cell (C-cell). The
can implement more than 4,000 combinatorial functions
of up to five inputs (Figure 1-3 on page 1-3).
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and active-low enable control
signals (Figure 1-3 on page 1-3). The R-cell registers
feature programmable clock polarity selectable on a
register-by-register
basis.
This
provides
additional
flexibility (e.g., easy mapping of dual-data-rate functions
into the FPGA) while conserving valuable clock resources.
The clock source for the R-cell can be chosen from the
hardwired clocks, routed clocks, or internal logic.
Two C-cells, a single R-cell, and two Transmit (TX) and two
Receive (RX) routing buffers form a Cluster, while two
Clusters comprise a SuperCluster (Figure 1-4 on page 1-3).
Each SuperCluster also contains an independent Buffer (B)
module, which supports buffer insertion on high-fanout
nets by the place-and-route tool, minimizing system
delays while improving logic utilization.
The logic modules within the SuperCluster are arranged
so that two combinatorial modules are side-by-side,
giving a C–C–R – C–C–R pattern to the SuperCluster. This
C–C–R
pattern
enables
efficient
implementation
(minimum delay) of two-bit carry logic for improved
arithmetic performance (Figure 1-5 on page 1-3).
The AX architecture is fully fracturable, meaning that if
one or more of the logic modules in a SuperCluster are
used by a particular signal path, the other logic modules
are still available for use by other paths.
At the chip level, SuperClusters are organized into core
tiles, which are arrayed to build up the full chip. For
example, the AX1000 is composed of a 3x3 array of nine
core tiles. Surrounding the array of core tiles are blocks
of I/O Clusters and the I/O bank ring (Table 1-1 on
page 1-3). Each core tile consists of an array of 336
SuperClusters and four SRAM blocks (176 SuperClusters
and three SRAM blocks for the AX250). The SRAM blocks
are arranged in a column on the west side of the tile
Figure 1-2 Axcelerator Family Interconnect Elements
相關(guān)PDF資料
PDF描述
AX1000-2BG729IX79 FPGA, 12096 CLBS, 612000 GATES, 870 MHz, PBGA729
AX1000-2BG729I FPGA, 12096 CLBS, 612000 GATES, 870 MHz, PBGA729
AX1000-2BG729X79 FPGA, 12096 CLBS, 612000 GATES, 870 MHz, PBGA729
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AX1000-1FGG896B 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs
AX1000-1FGG896I 功能描述:IC FPGA AXCELERATOR 1M 896-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門(mén)陣列) 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA(23x23)
AX1000-1FGG896M 制造商:Microsemi Corporation 功能描述:FPGA Axcelerator Family 612K Gates 12096 Cells 763MHz 0.15um (CMOS) Technology 1.5V 896-Pin FBGA 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 612K GATES 12096 CELLS 763MHZ 0.15UM 1.5V 8 - Trays
AX1000-1FGG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs
AX1000-1LG624M 制造商:Microsemi Corporation 功能描述:AXCELERATOR-1,000,000 GATES - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 418 I/O 624LGA