參數(shù)資料
型號(hào): AX1000-2FGG484
元件分類: FPGA
英文描述: FPGA, 12096 CLBS, 612000 GATES, 870 MHz, PBGA484
封裝: 1 MM PITCH, FBGA-484
文件頁(yè)數(shù): 180/230頁(yè)
文件大?。?/td> 6485K
代理商: AX1000-2FGG484
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Axcelerator Family FPGAs
v2.8
2-39
Differential Standards
Physical Implementation
Implementing differential I/O standards requires the
configuration of a pair of external I/O pads, resulting in a
single internal signal. To facilitate construction of the
differential pair, a single I/O Cluster contains the
resources for a pair of I/Os. Configuration of the I/O
Cluster as a differential pair is handled by Actel's
Designer
software
when
the
user
instantiates
a
differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the
embedded Input Register (InReg), Output Register
(OutReg), Enable Register (EnReg), and Double Data
Rate
(DDR).
However,
there
is
no
support
for
bidirectional I/Os or tristates with these standards.
LVDS
Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a
high-speed, differential I/O standard. It requires that one
data bit is carried through two signal lines, so two pins
are needed. It also requires an external resistor
termination. The voltage swing between these two
signal lines is approximately 350 mV.
The LVDS circuit consists of a differential driver
connected to a terminated receiver through a constant-
impedance transmission line. The receiver is a wide-
common-mode-range
differential
amplifier.
The
common-mode range is from 0.2V to 2.2V for a
differential input with 400 mV swing.
To implement the driver for the LVDS circuit, drivers from
two adjacent I/O cells are used to generate the
differential signals (note that the driver is not a current-
mode driver). This driver provides a nominal constant
current of 3.5 mA. When this current flows through a
100
Ω termination resistor on the receiver side, a voltage
swing of 350 mV is developed across the resistor. The
direction of the current flow is controlled by the data fed
to the driver.
An external-resistor network (three resistors) is needed
to reduce the voltage swing to about 350 mV. Therefore,
four external resistors are required, three for the driver
and one for the receiver.
Figure 2-25 LVDS Board-Level Implementation
140
Ω
100
Ω
ZO=50
Ω
ZO=50
Ω
165
Ω
165
Ω
+
P
N
P
N
INBUF_LVDS
OUTBUF_LVDS
FPGA
Table 2-55 DC Input and Output Levels
DC Parameter
Description
Min.
Typ.
Max.
Units
VCCI
1
Supply Voltage
2.375
2.5
2.625
V
VOH
Output High Voltage
1.25
1.425
1.6
V
VOL
Output Low Voltage
0.9
1.075
1.25
V
VODIFF
Differential Output Voltage
250
350
450
mV
VOCM
Output Common Mode Voltage
1.125
1.25
1.375
V
VICM
2
Input Common Mode Voltage
0.2
1.25
2.2
V
1. +/- 5%
2. Differential input voltage =+/-350mV.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AX1000-2FGG484I 功能描述:IC FPGA AXCELERATOR 1M 484-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Axcelerator 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP,帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP(75x75)
AX1000-2FGG676 功能描述:IC FPGA AXCELERATOR 1M 676-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA(23x23)
AX1000-2FGG676I 功能描述:IC FPGA AXCELERATOR 1M 676-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Axcelerator 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP,帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP(75x75)
AX1000-2FGG896 功能描述:IC FPGA AXCELERATOR 1M 896-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA(23x23)
AX1000-2FGG896B 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs