Detailed Specifications
2- 78
R e v i sio n 1 8
PLL Configurations
The following rules apply to the different PLL inputs and outputs:
Reference Clock
1. Global routed clocks (CLKE/F/G/H) or user-created clock network
2. CLK1 output of an adjacent PLL
3. [H]CLKxP (single-ended or voltage-referenced)
4. [H]CLKxP/[H]CLKxN pair (differential modes like LVPECL or LVDS)
Feedback Clock
1. Global routed clocks (CLKE/F/G/H) or user-created clock network
2. External [H]CLKxP/N I/O pad(s) from the adjacent PLL cell
3. An internal signal from the PLL block
Figure 2-50 Reference Clock Connections
Figure 2-51 Feedback Clock Connections
Non-clock
Pins
P
N
INBUF
PLL
RefCLK
PLL
RefCLK
PLL
CLK1
Regular, LVPECL, or LVDS IOPAD
Any macro from the core, except HCLK nets
For cascading
Logic
PLL
FB
PLL
PLLOUT/PLLRCLK
Any macro except HCLK macros