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參數(shù)資料
| 型號(hào)： | AX250-2FG256I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PBGA256 |
| 封裝： | 1 MM PITCH, FBGA-256 |
| 文件頁(yè)數(shù)： | 148/230頁(yè) |
| 文件大?。?/td> | 6485K |
| 代理商： | AX250-2FG256I |
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Axcelerator Family FPGAs
2- 10
v2.8
JTAG/Probe Pins
PRA/B/C/D
Probe A/B/C/D
The Probe pins are used to output data from any user-
defined design node within the device (controlled with
Silicon Explorer II). These independent diagnostic pins
can be used to allow real-time diagnostic output of any
signal
path
within
the
device.
The
pins’
probe
capabilities can be permanently disabled to protect
programmed design confidentiality. The probe pins are
of LVTTL output levels.
TCK
Test Clock
Test clock input for JTAG boundary-scan testing and
diagnostic probe (Silicon Explorer II).
TDI
Test Data Input
Serial
input
for
JTAG
boundary-scan
testing
and
diagnostic probe. TDI is equipped with an internal 10 k
Ω
pull-up resistor.
TDO
Test Data Output
Serial output for JTAG boundary-scan testing.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1
boundary-scan pins (TCK, TDI, TDO, TRST). TMS is
equipped with an internal 10 k
Ω pull-up resistor.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active-low input to
asynchronously initialize or reset the boundary scan circuit.
The TRST pin is equipped with a 10 k
Ω pull-up resistor.
Special Functions
LP
Low Power Pin
The LP pin controls the low power mode of Axcelerator
devices. The device is placed in the low power mode by
connecting the LP pin to logic high. To exit the low
power mode, the LP pin must be set Low. Additionally,
the LP pin must be set Low during chip powering-up or
chip powering-down operations. See "Low Power
Mode" on page 2-89 for more details.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
User I/Os2
Introduction
The Axcelerator family features a flexible I/O structure,
supporting a range of mixed voltages (1.5V, 1.8V, 2.5V,
and 3.3V) with its bank-selectable I/Os. Table 2-8 on
page 2-11 contains the I/O standards supported by the
Axcelerator
family,
and
compares the features of the different I/O standards.
Each I/O provides programmable slew rates, drive
strengths, and weak pull-up and weak pull-down circuits.
I/O standards, except 3.3V PCI and 3.3V PCI-X, are
capable of hot insertion. 3.3V PCI and 3.3V PCI-X are 5V
tolerant with the aid of an external resistor.
The input buffer has an optional user-configurable delay
element. The element can reduce or eliminate the hold
time requirement for input signals registered within the
I/O cell. The value for the delay is set on a bank-wide
basis. Note that the delay WILL be a function of process
variations as well as temperature and voltage changes.
Each I/O includes three registers: an input (InReg), an
output (OutReg), and an enable register (EnReg). I/Os are
organized into banks, and there are eight banks per
device — two per side (Figure 2-6 on page 2-15). Each I/O
bank has a common VCCI, the supply voltage for its I/Os.
For voltage-referenced I/Os, each bank also has a
common reference-voltage bus, VREF. While VREF must
have a common voltage for an entire I/O bank, its
location is user-selectable. In other words, any user I/O in
the bank can be selected to be a VREF.
The location of the VREF pin should be selected according
to the following rules:
Any pin that is assigned as a VREF can control a
maximum of eight user I/O pad locations in each
direction (16 total maximum) within the same I/O
bank.
I/O pad locations listed as no connects are counted
as part of the 16 maximum. In many cases, this
leads to fewer than eight user I/O package pins in
each direction being controlled by a VREF pin.
Dedicated I/O pins (GND, VCCI...) are counted as
part of the 16.
The two user I/O pads immediately adjacent on each
side of the VREF pin (four in total) may only be used
as an input. The exception is when there is a VCCI/
GND pair separating the VREF pin and the user I/O
pad location.
2. Do not use an external resister to pull the I/O above VCCI for a higher logic “1” voltage level. The desired higher logic “1”
voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above VCCI.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX250-2FG256 | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PBGA256 |
| AX250-2FG484I | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PBGA484 |
| AX250-2FG484 | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PBGA484 |
| AX250-2PQ208I | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PQFP208 |
| AX250-2PQ208 | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX250-2FG484 | 功能描述:IC FPGA AXCELERATOR 250K 484FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Axcelerator 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| AX250-2FG484I | 功能描述:IC FPGA AXCELERATOR 250K 484FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| AX250-2FG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-2FG896B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-2FG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
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