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參數(shù)資料
| 型號(hào)： | AX250-2FG484 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PBGA484 |
| 封裝： | 1 MM PITCH, FBGA-484 |
| 文件頁(yè)數(shù)： | 207/230頁(yè) |
| 文件大?。?/td> | 6485K |
| 代理商： | AX250-2FG484 |
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Axcelerator Family FPGAs
2- 64
v2.8
Functional Description
Figure 2-48 on page 2-63 illustrates a block diagram of
the PLL. The PLL contains two dividers, i and j, that allow
frequency scaling of the clock signal:
The i divider in the feedback path allows
multiplication of the input clock by integer factors
ranging from 1 to 64, and the resultant frequency
is available at the output of the PLL block.
The j divider divides the PLL output by integer
factors ranging from 1 to 64, and the divided clock
is available at CLK1.
The two dividers together can implement any
combination of multiplication and division up to a
maximum frequency of 1 GHz on CLK1. Both the
CLK1 and CLK2 outputs have a fixed 50/50 duty
cycle.
The output frequencies of the two clocks are given
by the following formulas (fREF is the reference
clock frequency):
fCLK1 = fREF * (DividerI) / (DividerJ)
EQ 2-4
fCLK2 = fREF * (DividerI)
EQ 2-5
CLK2 provides the PLL output directly—without
division
The input and output frequency ranges are selected by
LowFreq and Osc(2:0), respectively. These functions and
their possible values are detailed in Table 2-79.
The delay lines shown in Figure 2-48 on page 2-63 are
programmable. The feedback clock path can be delayed
(using the five DelayLine bits) relative to the reference
clock (or vice versa) by up to 3.75 ns in increments of
250 ps. Table 2-79 describes the usage of these bits. The
delay increments are independent of frequency, so this
results in phase changes that vary with frequency. The
delay value is highly dependent on VCC and the speed
grade.
Figure 2-49 on page 2-65 is a logical diagram of the
various control signals to the PLL and shows how the PLL
interfaces with the global and routing networks of the
FPGA. Note that not all signals are user-accessible. These
non-user-accessible signals are used by Actel's place-and-
route tool to control the configuration of the PLL. The
user gains access to these control signals either based
upon the connections built in the user's design or
through the special macros (Table 2-83 on page 2-67)
inserted into the design. For example, connecting the
macro PLLOUT to CLK2 will control the OUTSEL signal.
Table 2-79 PLL Interface Signals
Signal Name
Type
User Accessible
Allowable Values
Function
RefCLK
Input
Yes
Reference Clock for the PLL
FB
Input
Yes
Feedback port for the PLL
PowerDown
Input
Yes
PLL power down control
0
PLL powered down
1
PLL active
DIVI[5:0]
Input
Yes
1 to 64, in unsigned
binary notation offset
by -1
Sets value for feedback divider (multiplier)
DIVJ[5:0]
Input
Yes
Sets value for CLK1 divider
LowFreq
Input
Yes
Input frequency range selector
0
50–200 MHz
1
14–50 MHz
Osc[2:0]
Input
Yes
Output frequency range selector
XX0
400–1000 MHZ
001
200–400 MHZ
011
100–200 MHZ
101
50–100 MHZ
111
20–50 MHZ
DelayLine[4:0]
Input
Yes
–15 to +15
(increments), in signed-
and-magnitude binary
representation
Clock Delay (positive/negative) in increments of 250 ps, with
maximum value of ± 3.75 ns
FBMuxSel
Input
No
Selects the source for the feedback input
REFSEL
Input
No
Selects the source for the reference clock
OUTSEL
Input
No
Selects the source for the routed net output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX250-2PQ208I | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PQFP208 |
| AX250-2PQ208 | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PQFP208 |
| AX250-FG256I | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PBGA256 |
| AX250-FG256 | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PBGA256 |
| AX250-FG484I | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PBGA484 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX250-2FG484I | 功能描述:IC FPGA AXCELERATOR 250K 484FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| AX250-2FG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-2FG896B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-2FG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-2FG896M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
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