- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295120 > AX250-FG484 FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PBGA484 PDF資料下載
參數(shù)資料
| 型號(hào)： | AX250-FG484 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PBGA484 |
| 封裝： | 1 MM PITCH, FBGA-484 |
| 文件頁(yè)數(shù)： | 148/230頁(yè) |
| 文件大?。?/td> | 6485K |
| 代理商： | AX250-FG484 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)當(dāng)前第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)
Axcelerator Family FPGAs
2- 10
v2.8
JTAG/Probe Pins
PRA/B/C/D
Probe A/B/C/D
The Probe pins are used to output data from any user-
defined design node within the device (controlled with
Silicon Explorer II). These independent diagnostic pins
can be used to allow real-time diagnostic output of any
signal
path
within
the
device.
The
pins’
probe
capabilities can be permanently disabled to protect
programmed design confidentiality. The probe pins are
of LVTTL output levels.
TCK
Test Clock
Test clock input for JTAG boundary-scan testing and
diagnostic probe (Silicon Explorer II).
TDI
Test Data Input
Serial
input
for
JTAG
boundary-scan
testing
and
diagnostic probe. TDI is equipped with an internal 10 k
Ω
pull-up resistor.
TDO
Test Data Output
Serial output for JTAG boundary-scan testing.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1
boundary-scan pins (TCK, TDI, TDO, TRST). TMS is
equipped with an internal 10 k
Ω pull-up resistor.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active-low input to
asynchronously initialize or reset the boundary scan circuit.
The TRST pin is equipped with a 10 k
Ω pull-up resistor.
Special Functions
LP
Low Power Pin
The LP pin controls the low power mode of Axcelerator
devices. The device is placed in the low power mode by
connecting the LP pin to logic high. To exit the low
power mode, the LP pin must be set Low. Additionally,
the LP pin must be set Low during chip powering-up or
chip powering-down operations. See "Low Power
Mode" on page 2-89 for more details.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
User I/Os2
Introduction
The Axcelerator family features a flexible I/O structure,
supporting a range of mixed voltages (1.5V, 1.8V, 2.5V,
and 3.3V) with its bank-selectable I/Os. Table 2-8 on
page 2-11 contains the I/O standards supported by the
Axcelerator
family,
and
compares the features of the different I/O standards.
Each I/O provides programmable slew rates, drive
strengths, and weak pull-up and weak pull-down circuits.
I/O standards, except 3.3V PCI and 3.3V PCI-X, are
capable of hot insertion. 3.3V PCI and 3.3V PCI-X are 5V
tolerant with the aid of an external resistor.
The input buffer has an optional user-configurable delay
element. The element can reduce or eliminate the hold
time requirement for input signals registered within the
I/O cell. The value for the delay is set on a bank-wide
basis. Note that the delay WILL be a function of process
variations as well as temperature and voltage changes.
Each I/O includes three registers: an input (InReg), an
output (OutReg), and an enable register (EnReg). I/Os are
organized into banks, and there are eight banks per
device — two per side (Figure 2-6 on page 2-15). Each I/O
bank has a common VCCI, the supply voltage for its I/Os.
For voltage-referenced I/Os, each bank also has a
common reference-voltage bus, VREF. While VREF must
have a common voltage for an entire I/O bank, its
location is user-selectable. In other words, any user I/O in
the bank can be selected to be a VREF.
The location of the VREF pin should be selected according
to the following rules:
Any pin that is assigned as a VREF can control a
maximum of eight user I/O pad locations in each
direction (16 total maximum) within the same I/O
bank.
I/O pad locations listed as no connects are counted
as part of the 16 maximum. In many cases, this
leads to fewer than eight user I/O package pins in
each direction being controlled by a VREF pin.
Dedicated I/O pins (GND, VCCI...) are counted as
part of the 16.
The two user I/O pads immediately adjacent on each
side of the VREF pin (four in total) may only be used
as an input. The exception is when there is a VCCI/
GND pair separating the VREF pin and the user I/O
pad location.
2. Do not use an external resister to pull the I/O above VCCI for a higher logic “1” voltage level. The desired higher logic “1”
voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above VCCI.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX250-PQ208I | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PQFP208 |
| AX250-PQ208 | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PQFP208 |
| AX250-1CQ208M | FPGA, 2816 CLBS, 154000 GATES, 763 MHz, CQFP208 |
| AX250-1CQ352M | FPGA, 2816 CLBS, 154000 GATES, 763 MHz, CQFP352 |
| AX250-1FG256M | FPGA, 2816 CLBS, 154000 GATES, 763 MHz, PBGA256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX250-FG484I | 功能描述:IC FPGA AXCELERATOR 250K 484FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Axcelerator 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| AX250-FG484M | 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 154K GATES 2816 CELLS 649MHZ 0.15UM 1.5V 48 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 248 I/O 484FBGA |
| AX250-FG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-FG896B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-FG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。