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參數(shù)資料
| 型號： | AZHLT21 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Differential PECL to CMOS/TTL Translator |
| 中文描述： | 差分PECL的CMOS / TTL電翻譯 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 149K |
| 代理商： | AZHLT21 |
AZ100ELT21
Differential PECL to CMOS/TTL Translator
1630 S. STAPLEY DR., SUITE 125
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
3.5ns Typical Propagation Delay
Differential PECL Inputs
CMOS/TTL Outputs
Flow Through Pinouts
Operating Range of 3.0V to 5.5V
Direct Replacement for ON Semiconductor
MC100ELT21
Use AZ100ELT21 for 10K Applications
DESCRIPTION
The AZ100ELT21 is a differential PECL to CMOS/TTL translator. Because PECL (Positive ECL) levels are
used, only V
CC
and ground are required. The small outline 8-lead packaging and the single gate of the ELT21 makes
it ideal for those applications where space, performance and low power are at a premium.
The ELT21 provides a V
BB
output for single-ended use or a DC bias reference for AC coupling to the device.
For single-ended input applications, the V
BB
reference should be connected to one side of the D0/ˉˉ differential
input pair. The input signal is then fed to the other D0/ˉˉ input. The V
BB
pin should be used only as a bias for the
ELT21 as its sink/source capability is limited. When used, the V
BB
pin should be bypassed to ground via a 0.01
μ
F
capacitor.
NOTE: Specification in ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PACKAGE AVAILABILITY
PACKAGE
PART NO.
SOIC 8
AZ100ELT21D
SOIC 8 T&R
AZ100ELT21DR1
SOIC 8 T&R
AZ100ELT21DR2
TSSOP 8
AZ100ELT21T
TSSOP 8 T&R AZ100ELT21TR1
TSSOP 8 T&R AZ100ELT21TR2
MARKING
AZM100ELT21
AZM100ELT21
AZM100ELT21
AZHLT21
AZHLT21
AZHLT21
PIN DESCRIPTION
PIN
FUNCTION
CMOS/TTL Output
Differential Inputs
Positive Supply
Reference Voltage Output
Ground
No Connect
Q
D0, ˉˉ
V
CC
V
BB
GND
NC
8
5
6
7
4
3
2
1
VCC
Q
GND
NC
D0
VBB
D0
NC
PECL
CMOS/TTL
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