參數(shù)資料
型號(hào): BD3460FS-E2
廠商: Rohm Semiconductor
文件頁數(shù): 2/9頁
文件大?。?/td> 0K
描述: IC SOUND PROCESSOR 6CH 24-SSOP
標(biāo)準(zhǔn)包裝: 1
類型: 音量控制
應(yīng)用: 車載音頻
安裝類型: 表面貼裝
封裝/外殼: 24-SOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: BD3460FS-E2DKR
PI6C48533-01
3.3V Low Skew 1-to-4
Differential/LVCMOS to LVPECL Fanout Buffer
2
PS8737B
12/15/09
Pin Description
Name
Pin #
Type
Description
VEE
1
P
Connect to Negative power supply
CLK_EN
2
I_PU
Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx
outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 50KΩ pull-up.
CLK_
SEL
3
I_PD
Clock select input. When high, selects PCLK input. When low, selects CLK input. LVCMOS/
LVTTL level with 50KΩ pull-down.
CLK
4
I_PD
Non-inverting differential clock input
nCLK
5
I_PU
Inverting differential clock input
PCLK
6
I_PD
Non-inverting differential clock input
nPCLK
7
I_PU
Inverting differential clock input
NC
8, 9
Not connected
VCC
10, 13,
18
P
Connect to 3.3V.
nQ3,
Q3
11,
12
O
Differential output pair, LVPECL interface level.
nQ2,
Q2
14,
15
O
Differential output pair, LVPECL interface level.
nQ1,
Q1
16,
17
O
Differential output pair, LVPECL interface level.
nQ0,
Q0
19,
20
O
Differential output pair, LVPECL interface level.
Note:
1.
I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up
Pin Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
CIN
Input Capacitance
4
pF
R_pullup
Input Pullup Resistance
50
R_pulldown
Input Pulldown Resistance
50
Control Input Function Table(1)
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
Q0:Q3nQ0:nQ3
0
CLK, nCLK
Diasbled: Low
Diasbled: High
0
1
PCLK, nPCLK
Disabled: Low
Disabled: High
1
0
CLK, nCLK
Enabled
1
PCLK, nPCLK
Enabled
Note:
1.
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.
09-0110
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