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參數(shù)資料
| 型號： | BH16273DL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 16-bit D-type flip-flop |
| 中文描述： | ABT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 85K |
| 代理商： | BH16273DL |
Philips Semiconductors
Product specification
74ABT16273
74ABTH16273
16-bit D-type flip-flop
1998 Feb 27
6
AC SETUP REQUIREMENTS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF; R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
°
C
V
CC
= +5.0V
MIN
2.0
2.0
0
0
3.3
3.3
3.3
T
amb
= –40 to +85
°
C
V
CC
= +5.0V
±
0.5V
MIN
2.0
2.0
0
0
3.3
3.3
3.3
UNIT
TYP
1.0
1.0
–0.6
–0.6
1.2
1.0
1.1
t
S
(H)
t
S
(L)
t
h
(H)
t
h
(L)
t
W
(H)
t
W
(L)
t
W
(L)
Setup time, High or Low
nDx to nCP
Hold time, High or Low
nDx to nCP
Clock pulse width
High or Low
Master Reset pulse width, Low
Recovery time
nMR + nCP
3
ns
3
ns
1
ns
2
ns
t
REC
2
2.0
0.0
2.0
ns
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 2.7V
V
M
t
PLH
t
PHL
V
M
V
M
V
M
nCP
nQx
1/f
MAX
t
W
(H)
t
W
(L)
SH00056
V
OL
V
OH
0V
V
M
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
V
M
nMR
V
M
nQx
t
w
(L)
V
M
t
PHL
V
M
t
REC
nCP
SH00057
0V
0V
V
OH
V
OL
Waveform 2. Master Reset Pulse Width, Master Reset to Output
Delay and Master Reset to Clock Recovery Time
NOTE:
The shaded areas indicate when the input is
permitted to change for predictable output performance.
ééé
ééé
ééé
éééééééé
éééééééé
éééééééé
V
M
nDx
V
M
V
M
V
M
V
M
nCP
SH00058
V
M
0V
0V
Waveform 3. Data Setup and Hold Times
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