參數(shù)資料
型號: AD7854LARZ
廠商: Analog Devices Inc
文件頁數(shù): 10/28頁
文件大?。?/td> 0K
描述: IC ADC 12BIT PARALLEL LP 28-SOIC
標(biāo)準(zhǔn)包裝: 27
位數(shù): 12
采樣率(每秒): 100k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 30mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)偽差分,單極;1 個(gè)偽差分,雙極
產(chǎn)品目錄頁面: 779 (CN2011-ZH PDF)
AD7854/AD7854L
–18–
REV. B
Using The Internal (On-Chip) Reference
As in the case of an external reference the AD7854/AD7854L can
power up from one of two conditions, power-up after the sup-
plies are connected or power-up from a software power-down.
When using the on-chip reference and powering up when AVDD
and DVDD are first connected, it is recommended that the power-
up calibration mode be disabled as explained above. When using
the on-chip reference, the power-up time is effectively the time
it takes to charge up the external capacitor on the REFIN/
REFOUT pin. This time is given by the equation:
tUP = 9
× R × C
where R
≈ 150K and C = external capacitor.
The recommended value of the external capacitor is 100 nF;
this gives a power-up time of approximately 135 ms before a
calibration is initiated and normal operation should commence.
When CREF is fully charged, the power-up time from a software
power-down reduces to 5
s. This is because an internal switch
opens to provide a high impedance discharge path for the refer-
ence capacitor during power-down—see Figure 22. An added
advantage of the low charge leakage from the reference capacitor
during power-down is that even though the reference is being
powered down between conversions, the reference capacitor
holds the reference voltage to within 0.5 LSBs with throughput
rates of 100 samples/second and over with a full power-down
between conversions. A high input impedance op amp like the
AD707 should be used to buffer this reference capacitor if it is
being used externally. Note, if the AD7854/AD7854L is left in
its powered-down state for more than 100 ms, the charge on
CREF will start to leak away and the power-up time will increase.
If this longer power-up time is a problem, the user can use a
partial power-down for the last conversion so the reference
remains powered up.
SWITCH OPENS
DURING POWER-DOWN
TO OTHER CIRCUITRY
REFIN/OUT
EXTERNAL
CAPACITOR
ON-CHIP
REFERENCE
BUF
AD7854/
AD7854L
Figure 22. On-Chip Reference During Power-Down
POWER VS. THROUGHPUT RATE
The main advantage of a full power-down after a conversion is
that it significantly reduces the power consumption of the part
at lower throughput rates. When using this mode of operation,
the AD7854/AD7854L is only powered up for the duration of
the conversion. If the power-up time of the AD7854/AD7854L
is taken to be 5
s and it is assumed that the current during
power-up is 4.5 mA/1.5 mA typ, then power consumption as a
function of throughput can easily be calculated. The AD7854
has a conversion time of 4.6
s with a 4 MHz external clock,
and the AD7854L has a conversion time of 9
s with a 1.8 MHz
clock. This means the AD7854/AD7854L consumes 4.5 mA/
1.5 mA typ for 9.6
s/14 s in every conversion cycle if the parts
are powered down at the end of a conversion. The four graphs,
Figures 24, 25, 26 and 27, show the power consumption of the
AD7854 and AD7854L for VDD = 3 V as a function of through-
put. Table VII lists the power consumption for various throughput
rates.
Table VII. Power Consumption vs. Throughput
Power
Throughput Rate
AD7854
AD7854L
1 kSPS
130
W65 W
10 kSPS
1.3 mW
650
W
20 kSPS
2.6 mW
1.25 mW
50 kSPS
6.48 mW
3.2 mW
4MHz/1.8MHz
OSCILLATOR
AVDD DVDD
AIN(+)
AIN(–)
CREF1
CREF2
DB11
DB0
CONVST
AGND
DGND
CLKIN
REFIN/REFOUT
AD7854/
AD7854L
ANALOG
SUPPLY
+3V TO +5V
0.1 F
10 F
0.1 F
0.01 F
CONVERSION
START SIGNAL
0.1nF EXTERNAL REFERENCE
0.1 F ON-CHIP REFERENCE
0V TO 2.5V
INPUT
OPTIONAL
EXTERNAL
REFERENCE
CS
RD
WR
BUSY
AD780/
REF192
C/ P
HBEN
FULL POWER-DOWN
AFTER A CONVERSION
PMGT1 = 0
PMGT0 = 1
Figure 23. Typical Low Power Circuit
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